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octal, 12 - bit, 40/50/65 msps serial lvds 1.8 v a/d converter data sheet ad9222 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analo g devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3 113 ? 2006 C 2011 analog devices, inc. all rights reserved. features 8 adcs integrated into 1 package 114 mw adc power per channel at 65 msps snr = 70 db (to nyquist) enob = 11.3 bits sfdr = 80 dbc excellent linearity : dnl = 0.3 lsb (typical) , inl = 0.4 lsb (typical) serial lvds (ansi - 644, default) low power , r educ ed signal option (similar ieee 1596.3 ) data and frame clock outputs 325 mhz full - power analog bandwidth 2 v p - p input voltage range 1.8 v supply operation serial port control full - chip and individual - channel power - down modes flexible bit orientation b uilt - in and custom digital test pattern generation programmable clock and data alignment programmable output resolution standby mode applications medical imaging and nondestructive ultrasound porta ble ultrasound and digital beam - forming systems quadrature radio receivers diversity radio receivers tape drives optical networking test equipment general description the ad9222 is an octal, 12 - bit, 40/50 /65 msps analog - to - digital converter (adc) with an on - chip sampl e - and - hold circuit designed for low cost, low power, small size, and ease of use. the product operates at a conversion rate of up to 65 msps and is optimized for outstanding dynamic performance and low power in applications where a small package size is cr itical. the adc requires a single 1.8 v power supply and lvpecl - / cmos - /lvds - compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. the adc automatically multiplies the sa mple rate clock for the appropriate lvds serial data rate. a data clock output (dco) for capturing data on the output and a frame clock output (fco) for signaling a new outpu t byte are provided. individual - channel power - down is supported and typically co nsumes less than 2 mw when all channels are disabled. functional block dia gram s e r i a l l v d s r e f select a d9222 a g n d v i n ? a v i n + a v i n ? b v i n + b v i n ? d v i n + d v i n ? c v i n + c sense vref a v d d dr v d d 1 2 1 2 1 2 1 2 p d w n r e f t r e f b d ? a d + a d ? b d + b d ? d d + d d ? c d + c fco ? fco + dco + dco ? c l k+ dr g n d c l k? s e r i a l p o r t i n t e r f a ce c s b s c l k/ dtp s d i o/ odm rb i a s s e r i a l l v d s s e r i a l l v d s s e r i a l l v d s adc adc adc adc d a t a r a t e m u l t i p li e r 0.5v s e r i a l l v d s v i n ? e v i n + e v i n ? f v i n + f v i n ? h v i n + h v i n ? g v i n + g 1 2 1 2 1 2 1 2 d ? e d + e d ? f d + f d ? h d + h d ? g d + g s e r i a l l v d s s e r i a l l v d s s e r i a l l v d s adc adc adc adc 05967-001 figure 1. the adc contains several features designed to maximize flexibility and minimize sy stem cost, such as programmable clock and data alignment and programmable digital test pattern generation. the available digital test patterns include built - in deterministic and pseudorandom patterns, along with custom user - defined test patterns entered via the serial port interface (spi ). the ad9222 is available in a n rohs compliant , 64 - l e a d l f c s p. i t i s specified over the industrial temperature range of ?40 c to +85 c. product highlights 1. small footprint. eight adcs are contained in a small, space - saving package . 2. l ow power of 114 mw/channel at 65 msps. 3. ease of use. a data clock output (dco) is provided that operates at frequencies of up to 3 9 0 mhz and supp orts double data rate (ddr) operation. 4. user flexibility. the spi control offers a wide range of flexible features to meet specific system requirements. 5. pin - compatible family. th is includes the ad9212 (10 - bit) a nd ad9252 (14 - bit).
ad9222 data sheet rev. f | page 2 of 60 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac specifications .......................................................................... 4 digital specifications ................................................................... 5 switching specifications .............................................................. 6 timing diagrams .............................................................................. 7 absolute maximum ratings ............................................................ 9 thermal impedance ..................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 equivalent circuits ......................................................................... 12 typical perfor mance characteristics ........................................... 14 theory of operation ...................................................................... 21 analog input considerations ................................................... 21 clock input considerations ...................................................... 24 serial port interface (spi) .............................................................. 33 hardware interface ..................................................................... 34 memory map .................................................................................. 36 reading the memory map table .............................................. 36 reserved locations .................................................................... 36 default values ............................................................................. 36 logic levels ................................................................................. 36 evaluation board ............................................................................ 40 power supplies ............................................................................ 40 input signals ................................................................................ 40 output signals ............................................................................ 40 default operation and jumper selection settings ................. 41 alternative analog input drive configuration ...................... 42 outline dime nsions ....................................................................... 59 ordering guide .......................................................................... 59 revision history 12/11 rev e to rev. f changes to figure 86 ...................................................................... 41 changes to ordering guide .......................................................... 59 1 1 /11 rev. d to rev. e changes to out put signals section .............................................. 41 changes to figure 86 ...................................................................... 41 changes to ordering guide .......................................................... 60 4/10 rev. c to rev. d changes to address 16 in table 16 ............................................... 38 updated outline dimensions ....................................................... 59 changes to ordering guide .......................................................... 59 1/ 10 rev. b to rev. c updated outline dimensions ....................................................... 59 changes to ordering guide .......................................................... 60 7 /09 rev. a to rev. b changes to figure 5 ........................................................................ 10 changes to figure 61 and figure 62 ............................................. 23 changes to figure 79 and figure 80 ............................................. 31 updated outline dimensions ....................................................... 59 changes to ordering guide .......................................................... 59 8 /07 rev. 0 to rev. a added 65 msps m odels .................................................... universal chan ges to features .......................................................................... 1 changes to product highlights ....................................................... 1 changes to figure 2 to figure 4 ....................................................... 7 added figure 21 to figure 24, figure 27, figure 28, figure 30, figure 32, figure 37, figure 38, figure 40, figure 42, figure 44, figure 46, figure 48, and figure 51 .............................................. 15 ad ded figure 5 6 and figure 58 .................................................... 22 added figure 70 ............................................................................. 25 added figure 72 ............................................................................. 26 added figure 74 ............................................................................. 27 added figure 76 and figure 78 .................................................... 28 changes to digital outputs and timing section ....................... 28 changes to table 9 endnote .......................................................... 29 added table 10 ............................................................................... 30 changes to rbias pin section ..................................................... 31 delete d f igure 56 and figure 57 ................................................... 27 changes to table 15 ....................................................................... 35 change to input signals section ................................................... 40 change to output signals section ................................................ 40 changes to figure 86 ...................................................................... 40 changes to default operation and jumper selection settings section ............................................................................... 41 changes to alternative analog input co nfiguration section ......... 42 added figure 88 and figure 89 .................................................... 42 change to figure 92 ....................................................................... 45 changes to table 17 ....................................................................... 54 updated outline dimensions ....................................................... 59 changes to ordering guide .......................................................... 60 9/06 re vision 0: initial version
data sheet ad9222 rev. f | page 3 of 60 specifications av dd = 1.8 v, drvdd = 1.8 v, 2 v p - p different ial input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 1 . ad9222 - 40 ad9222 - 50 ad9222 - 65 parameter 1 temp min typ max min typ max min typ max unit resolution 12 12 12 bits accuracy no missing codes full guaranteed guaranteed guaranteed offset error full 1 8 1 8 1 8 mv offset matching full 3 8 3 8 3 8 mv gain error full 0.4 1.2 1.5 2.5 3.5 5 % fs gain matching full 0.3 0.7 0.3 0.7 0.4 0.8 % f s differential nonlinearity (dnl) full 0.25 0.5 0.3 0.65 0.25 0.6 lsb integral nonlinearity (inl) full 0.4 1 0.4 1 0.4 1 lsb temperature drift offset error full 2 2 2 ppm/ c gain error full 17 17 17 ppm/ c reference voltage (1 v mode) full 21 21 21 ppm/ c reference output voltage error (vref = 1 v) full 2 30 2 30 2 30 mv load regulation @ 1.0 ma (vref = 1 v) full 3 3 3 mv input resistance full 6 6 6 k ? analog inputs differential input voltage range (vref = 1 v) full 2 2 2 v p - p common - mode voltage full avdd/2 avdd/2 avdd/2 v differential input capacitance full 7 7 7 pf analog bandwidth, full power full 325 325 325 mhz po wer supply avdd full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v iavdd full 338 348.5 357.5 367.5 450 470 ma idrvdd full 51 53.6 53.5 56.2 56.6 60.5 ma total power dissipation (including out put drivers) full 700 722 740 760 910 950.5 mw power - down dissipation full 2 11 2 11 2 11 mw standby dissipation 2 full 83 89 100 mw crosstalk full ?90 ?90 ?90 db crosstalk (overrange condition) 3 full ?90 ?90 ?90 db 1 see th e an - 835 application note , understanding high speed adc testing and evaluation , for a c omplete set of definitions and how these t est s were completed. 2 this c an be controlled via spi. 3 overr ange condition is specific with 6 db of the full - scale input range.
ad9222 data sheet rev. f | page 4 of 60 ac specifi cations avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 2 . ad9222 - 40 ad9222 - 50 ad9222 - 65 parameter 1 temp min typ max min typ max min typ max unit signal - to - noise ratio (snr) f in = 2.4 mhz full 70.3 70.4 70.3 db f in = 19.7 mhz full 69.5 70.3 69.5 70.3 68.5 70.0 db f in = 35 mhz full 69.9 70.0 69.8 db f in = 70 mhz full 68.8 69.0 69.5 db signal - to - noise and distort ion ratio (sinad) f in = 2.4 mhz full 70.0 70.0 69.5 db f in = 19.7 mhz full 68.7 70.0 68.5 70.0 66.8 69.4 db f in = 35 mhz full 69.5 69.8 69.3 db f in = 70 mhz full 68.0 68.5 69 db effective number of bits (enob) f in = 2.4 mhz full 11.38 11.4 11. 4 bits f in = 19.7 mhz full 11.25 11.38 11.25 11.38 11.1 11.3 4 bits f in = 35 mhz full 11.32 11.33 11.3 0 bits f in = 70 mhz full 11.14 11.17 11.25 bits spurious - free dynamic range (sfdr) f in = 2.4 mhz full 85 85 83 dbc f in = 19.7 mhz full 73 85 73 84 70.5 80 dbc f in = 35 mhz full 80 83 80 dbc f in = 70 mhz full 76 77 75 dbc worst harmonic (second or third) f in = 2.4 mhz full ?85 ?85 ? 83 dbc f in = 19.7 mhz full ?85 ?74 ?84 ?73 ? 80 ? 70.5 dbc f in = 35 mhz full ?80 ?83 ? 80 dbc f in = 70 mhz full ?76 ?77 ? 75 dbc worst other (excluding second or third) f in = 2.4 mhz full ?92 ?92 ? 90 dbc f in = 19.7 mhz full ?92 ?80 ?92 ?80 ? 90 ? 80 dbc f in = 35 mhz full ?92 ?92 ? 90 dbc f in = 70 mhz full ?90 ?90 ? 85 dbc two - tone intermodulation distortion (imd) ain1 and ain2 = ?7.0 dbfs f in1 = 15 mhz, f in2 = 16 mhz 25c 80.0 80.0 80.0 dbc f in1 = 70 mhz, f in2 = 71 mhz 25c 77.0 77.0 75.0 dbc 1 see th e an - 835 application note , understanding high speed adc testing and evaluation , f or a complete set of definitions and how these t est s were completed.
data sheet ad9222 rev. f | page 5 of 60 digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 3 . ad9222 - 40 ad9222 - 50 ad9222 - 65 parameter 1 temp min typ max min typ max min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl cmos/lvds/lvpecl cmos/lvds/lvpecl differential input voltage 2 full 250 250 250 m v p - p input common - mode voltage full 1.2 1.2 1.2 v input resistance (differential) 25c 20 20 20 k ? input capacitance 25c 1.5 1.5 1.5 pf logic inputs (pdwn, sclk/dtp) logic 1 voltage full 1.2 3.6 1.2 3.6 1.2 3.6 v log ic 0 voltage full 0 0.3 0.3 0.3 v input resistance 25c 30 30 30 k ? input capacitance 25c 0.5 0.5 0.5 pf logic input (csb) logic 1 voltage full 1.2 3.6 1.2 3.6 1.2 3.6 v logic 0 voltage full 0 0.3 0.3 0.3 v input resistance 25c 70 70 70 k ? input capacitance 25c 0.5 0.5 0.5 pf logic input (sdio/odm) logic 1 voltage full 1.2 drvdd + 0.3 1.2 drvdd + 0.3 1.2 drvdd + 0.3 v logic 0 voltage full 0 0.3 0 0.3 0 0.3 v input resistance 25c 30 30 30 k ? input capacitance 25c 2 2 2 pf logic output (sdio/odm) 3 logic 1 voltage (i oh = 800 a) full 1.79 1.79 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 0.05 0.05 v digital outputs (d + x , d ? x ), (ansi - 644) 1 logic compliance lvds lvds lvds differential output voltage (v od ) full 247 454 247 454 247 454 mv output offset voltage (v os ) full 1.125 1.375 1.125 1.375 1.125 1.375 v output coding (d efault) offset binary offset binary offset binary digital outputs (d + x , d ? x ), (low power, reduced signal option) 1 logic compliance lvds lvds lvds differential output voltage (v od ) full 150 250 150 250 150 250 mv output offset voltage (v os ) full 1.10 1.30 1.10 1. 30 1.10 1.30 v output coding (default) offset binary offset binary offset binary 1 see th e an - 835 application note , understanding high speed adc testing and evaluation , for a c omplete set of definitions and how these t est s were completed. 2 this is specified for lvds and lvpecl only. 3 this is specified for 13 sdio pins sharing the same connection.
ad9222 data sheet rev. f | page 6 of 60 switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 4 . ad9222 - 40 ad9222 - 50 ad9222 - 65 parameter 1 temp min typ max min typ max min typ max unit clock 2 maximum clock rate full 40 50 65 msps minimum clock rate full 10 10 10 msps clock pulse width high (t eh ) full 12.5 10.0 7.5 ns clock pulse width low (t el ) full 12.5 10.0 7.5 ns output parameters 2 , 3 propagation delay (t pd ) full 1.5 2.3 3.1 1.5 2.3 3.1 1.5 2.3 3.1 ns rise time (t r ) (20% to 8 0%) full 300 300 300 ps fall time (t f ) (20% to 80%) full 300 300 300 ps fco propagation delay (t fco ) full 1.5 2.3 3.1 1.5 2.3 3.1 1.5 2.3 3.1 ns dco propagation delay (t cpd ) 4 full t fco + (t sample /24) t fco + (t sample /24) t fco + (t sam ple /24) ns dco to data delay (t data ) 4 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps dco to fco delay (t frame ) 4 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps data to data skew (t data - max ? t data - min ) full 50 200 50 200 50 200 ps wake - up time (standby) 25c 600 600 600 ns wake - up time (power - down) 25c 375 375 375 s pipeline latency full 8 8 8 clk cycles aperture aperture delay (t a ) 25c 750 750 750 ps aperture uncertainty (jitter) 25c <1 <1 <1 ps rms out - of - ran ge recovery time 25c 1 1 1 clk cycles 1 see t he an - 835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 thi s c an be adjusted via the spi interface. 3 measurements were made using a part soldere d to fr4 ma terial. 4 t sample /24 is based on the number of bits divided by 2 because the dela ys are based on half duty cycles.
data sheet ad9222 rev. f | page 7 of 60 timing diagrams dco? dco+ d ? x d + x fco? fco+ clk? clk+ msb n ? 9 d10 n ? 9 d9 n ? 9 d8 n ? 9 d7 n ? 9 d6 n ? 9 d5 n ? 9 d4 n ? 9 d3 n ? 9 d2 n ? 9 d1 n ? 9 d0 n ? 9 d10 n ? 8 msb n ? 8 n ? 1 n t da t a t frame t fco t pd t cpd t eh t a t el 05967-002 vin x figure 2 . 12 - bit data serial stream , msb first (default) dc o+ dc o? c l k+ f c o+ f c o? d ? x d + x c l k? m s b n ? 9 n ? 1 n d8 n ? 9 d7 n ? 9 d5 n ? 9 t da t a t frame t fco t pd d4 n ? 9 d6 n ? 9 d8 n ? 8 d7 n ? 8 d5 n ? 8 d6 n ? 8 d3 n ? 9 d1 n ? 9 m s b n ? 8 d0 n ? 9 d2 n ? 9 t cpd t eh t a t el 05967-003 vin x figure 3 . 10 - bit data serial stream , msb first
ad9222 data sheet rev. f | page 8 of 60 dco? dco+ d ? x d + x fco? fco+ vin x clk? clk+ lsb n ? 9 d0 n ? 9 d1 n ? 9 d2 n ? 9 d3 n ? 9 d4 n ? 9 d5 n ? 9 d6 n ? 9 d7 n ? 9 d8 n ? 9 d9 n ? 9 d10 n ? 9 d0 n ? 8 lsb n ? 8 n ? 1 t a n t da t a t frame t fco t pd t cpd t eh t el 05967-004 figure 4 . 12 - bit data serial stream, lsb first
data sheet ad9222 rev. f | page 9 of 60 absolute maximum rat ings table 5 . parameter with respect to rating electrical avdd agnd ?0.3 v to +2.0 v drvdd drgnd ?0.3 v to +2.0 v agnd drgnd ?0.3 v to +0.3 v avdd drvdd ?2.0 v to +2.0 v digital outputs (d + x , d ? x , dco+, dco?, fco+, fco?) drgnd ?0.3 v to +2.0 v clk+, clk? agnd ?0.3 v to +3.9 v vin + x , vin ? x agnd ?0.3 v to +2. 0 v sdio/odm agnd ?0.3 v to +2.0 v pdwn, sclk/dtp, csb agnd ?0.3 v to +3.9 v reft, refb, rbias agnd ?0.3 v to +2.0 v vref, sense agnd ?0.3 v to +2.0 v environmental operating temperature range (ambient) ?40 c to +85 c maximum junction temperatu re 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ?65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal impe dance table 6 . air flow velocity (m/s) ja 1 jb jc 0.0 17.7c/w 1.0 15.5c/w 8.7c/w 0.6c/w 2.5 13.9c/w 1 ja for a 4 - layer pcb with solid ground plane (simulated). exposed pad soldered to pcb. esd caution
ad9222 data sheet rev. f | page 10 of 60 pin configuration an d function descripti ons 05967-005 pin 1 indic a t or 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d ? g d + g d ? f d + f d ? e d + e dco? dco+ fco? fco+ d ? d d + d d ? c d + c d ? b d + b 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vin + f vin ? f a vdd vin ? e vin + e a vdd reft refb vref sense rbias vin + d vin ? d a vdd vin ? c vin + c 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 a vdd vin + g vin ? g a vdd vin ? h vin + h a vdd a vdd clk? clk+ a vdd a vdd drgnd dr vdd d ? h d + h a vdd vin + b vin ? b a vdd vin ? a vin + a a vdd pdwn csb sdio/odm sclk/dt p a vdd drgnd dr vdd d + a d ? a 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad9222 t op view (not to scale) exposed paddle, pin 0 (bottom of package) notes 1. the exposed pad must be connected to analog ground figure 5 . 64 - lead lfcsp pin configuration, top view table 7 . pin function descriptions pin no. mnemonic description 0 agnd analog ground (exposed paddle) 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62 avdd 1.8 v analog suppl y 13, 36 drgnd digital output driver ground 14, 35 drvdd 1.8 v digital output driver supply 2 vin + g adc g analog input true 3 vin ? g adc g analog input complement 5 vin ? h adc h analog input complement 6 vin + h adc h analog input true 9 clk? input clock complement 10 clk+ input clock true 15 d ? h adc h digital output c omplement 16 d + h adc h digital output true 17 d ? g adc g digital output complement 18 d + g adc g digital output true 19 d ? f adc f digital output complement 20 d + f adc f digital output true 21 d ? e adc e digital output complement 22 d + e adc e digital output true 23 dco? data clock digital out put complement 24 dco+ data clock digital output true 25 fco? frame clock digital output complement 26 fco+ frame clock digital output true 27 d ? d adc d digital output complement 28 d + d adc d digital output true 29 d ? c adc c digital output comp lement 30 d + c adc c digital output true 31 d ? b adc b digital output complement 32 d + b adc b digital output true
data sheet ad9222 rev. f | page 11 of 60 pin no. mnemonic description 33 d ? a adc a digital output complement 34 d + a adc a digital output true 38 sclk/dtp serial clock/digital test pattern 39 sdio/o dm serial data input - output/output driver mode 40 csb chip select bar 41 pdwn power down 43 vin + a adc a analog input true 44 vin ? a adc a analog input complement 46 vin ? b adc b analog input complement 47 vin + b adc b analog input true 49 vin + c adc c analog input true 50 vin ? c adc c analog input complement 52 vin ? d adc d analog input complement 53 vin + d adc d analog input true 54 rbias external resistor to set the internal adc core bias current 55 sense reference mode selection 56 vref voltage reference input/output 57 refb differential reference (negative) 58 reft differential reference (positive) 60 vin + e adc e analog input true 61 vin ? e adc e analog input complement 63 vin ? f adc f analog input complement 64 vin + f ad c f analog input true
ad9222 data sheet rev. f | page 12 of 60 equivalent circuits vin x 05967-006 figure 6 . equivalent analog input circuit 10? 10k? 10k? clk? 10? 1.25v clk+ 05967-007 figure 7 . equivalent clock input circuit sdio/odm 350? 30k? 05967-008 figure 8 . equivalent sdio/odm input circu it dr vdd drgnd d? d+ v v v v 05967-009 figure 9 . equivalent digital output circuit sclk/dt p and pdwn 30k? 1k? 05967-010 figure 10 . equivalent sclk/dtp and pdwn input circuit 100? rbias 05967-011 figure 11 . equivalent rbias circuit
data sheet ad9222 rev. f | page 13 of 60 csb 70k? 1k? a vdd 05967-012 figure 12 . equivalent csb input circuit sense 1k? 05967-013 figure 13 . equivalent sense circuit vref 6k ? 05967-014 figure 14 . equivalent vref circuit
ad9222 data sheet rev. f | page 14 of 60 typical performance characteristics 05967-015 frequency (mhz) amplitude (dbfs) ?120 0 0 20 ?100 ?80 ?60 ?40 ?20 2 4 6 8 10 12 14 16 18 ain = ?0.5dbfs snr = 70.79db enob = 1 1.47 bits sfdr = 84.71dbc figure 15 . single - ton e 32k fft with f in = 2.3 mhz, ad9222 - 40 05967-016 frequency (mhz) amplitude (dbfs) ?120 0 0 20 ?100 ?80 ?60 ?40 ?20 2 4 6 8 10 12 14 16 18 ain = ?0.5dbfs snr = 70.32db enob = 1 1.39 bits sfdr = 84.28dbc figure 16 . single - tone 32k fft with f in = 19.7 mhz, ad9222 - 40 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 amplitude (dbfs) frequency (mhz) ain = ?0.5dbfs snr = 70.72db enob = 11.45 bits sfdr = 85.79dbc 05967-017 figure 17 . single - tone 32k fft with f in = 2.3 mhz, ad9222 - 50 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 amplitude (dbfs) frequency (mhz) ain = ?0.5dbfs snr = 70.35db enob = 11.40 bits sfdr = 83.86dbc 05967-018 figure 18 . single - tone 32k fft with f in = 35 mhz, ad9222 - 50 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 amplitude (dbfs) frequency (mhz) ain = ?0.5dbfs snr = 70.02db enob = 11.45 bits sfdr = 86.3dbc 05967-019 figure 19 . single - tone 32k fft with f in = 70 mhz, ad9222 - 50 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 amplitude (dbfs) frequency (mhz) ain = ?0.5dbfs snr = 69.25db enob = 11.21 bits sfdr = 72.85dbc 05967-020 figure 20 . single - tone 32k fft with f in = 120 mhz, ad9222 - 50
data sheet ad9222 rev. f | page 15 of 60 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) a i n = ?0 . 5 db fs s nr = 70 . 21 db e n o b = 11 . 31 b i ts s fdr = 82 . 37 db c 05967-085 figure 21 . single - tone 32k fft with f in = 2.3 mhz, ad9222 - 65 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) a i n = ?0 . 5 db fs s nr = 69.8db e n o b = 11 . 22 b i ts s fdr = 80.61d b c 05967-086 figure 22 . single - tone 32k fft with f in = 35 mhz, ad9222 - 65 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) a i n = ?0 . 5 db fs s nr = 69.65db e n o b = 11 . 07 b i ts s fdr = 74.79d b c 05967-087 figure 23 . single - tone 32k fft with f in = 70 mhz, ad9222 - 65 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) a i n = ?0 . 5 db fs s nr = 68.67db e n o b = 1 0.79 b i ts s fdr = 71.49d b c 05967-088 figure 24 . single - tone 32k fft with f in = 120 mhz, ad9222 - 65 100 90 95 85 80 75 70 65 60 10 50 45 40 35 30 25 20 15 snr/sfdr (db) encode (msps) 2v p-p, sfdr 2v p-p, snr 05967-021 figure 25 . snr/sfdr vs. f sample , f in = 2.61 mhz, ad9222 - 50 90 85 80 75 70 65 60 10 50 45 40 35 30 25 20 15 snr/sfdr (db) encode (msps) 2v p-p, sfdr 2v p-p, snr 05967-022 figure 26 . snr/sfdr vs. f sample , f in = 20.1 mhz, ad9222 - 50
ad9222 data sheet rev. f | page 16 of 60 snr/sfdr (db) encode (msps) 60 65 70 75 80 85 90 95 100 10 15 20 25 30 35 40 45 50 55 60 65 2v p-p, sfdr 2v p-p, snr 05967-089 figure 27 . snr/sfdr vs. f sample , f in = 2.3 mhz, ad9222 - 65 snr/sfdr (db) encode (msps) 60 65 70 75 80 85 90 10 15 20 25 30 35 40 45 50 55 60 65 2v p-p, sfdr 2v p-p, snr 05967-090 figure 28 . snr/sfdr vs. f sample , f in = 19.7 mhz, ad9222 - 65 100 90 80 70 60 50 40 30 20 10 0 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (db) input amplitude (dbfs) 80db reference 2v p-p, sfdr 2v p-p, snr 05967-023 figure 29 . snr/sfdr vs. analog input level, f in = 10 .3 mhz, ad9222 - 50 2v p-p, snr 2v p-p, sfdr snr/sfdr (db) input amplitude (dbfs) 0 10 20 30 40 50 60 70 80 90 ?60 ?50 ?40 ?30 ?20 ?10 0 80db reference line 05967-091 figure 30 . snr/sfdr vs. analog input level, f in = 10.3 mhz, ad9222 - 65 100 90 80 70 60 50 40 30 20 10 0 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (db) input amplitude (dbfs) 80db reference 2v p-p, sfdr 2v p-p, snr 05967-024 figure 31 . snr/sfdr vs. analog input level, f in = 35 mhz, ad9222 - 50 2v p-p, snr 2v p-p, sfdr snr/sfdr (db) input amplitude (dbfs) 0 10 20 30 40 50 60 70 80 90 ?60 ?50 ?40 ?30 ?20 ?10 0 80db reference line 05967-092 figure 32 . s nr/sfdr vs. analog input level, f in = 35 mhz, ad9222 - 65
data sheet ad9222 rev. f | page 17 of 60 0 ?120 ?100 ?80 ?60 ?40 ?20 0 2 4 6 8 10 12 14 16 18 20 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 89.87db imd2 = 96.07dbc imd3 = 90.16dbc 05967-025 figure 33 . two - tone 32k fft with f in1 = 15 mhz and f in2 = 16 mhz, ad9222 - 40 0 ?120 ?100 ?80 ?60 ?40 ?20 0 2 4 6 8 10 12 14 16 18 20 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 77.24db imd2 = 91.66dbc imd3 = 77.72dbc 05967-026 figure 34 . two - tone 32k fft with f in1 = 70 mhz and f in2 = 71 mhz , ad9222 - 40 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 84.49db imd2 = 85.83dbc imd3 = 84.54dbc 05967-027 figure 35 . two - tone 32k fft with f in1 = 15 mhz and f in2 = 16 mhz, ad9222 - 50 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 80.42db imd2 = 83.92dbc imd3 = 80.60dbc 05967-032 figure 36 . two - tone 32k fft with f in1 = 70 mhz and f in2 = 71 mhz, ad9222 - 50 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 79.5db imd2 = 80.0dbc imd3 = 84.1dbc 05967-093 figure 37 . two - tone 32k fft with f in1 = 15 mhz and f in2 = 16 mhz, ad9222 - 65 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 75.2db imd2 = 79.3dbc imd3 = 75.1dbc 05967-094 figure 38 . two - tone 32k fft with f in1 = 70 mhz and f in2 = 71 mhz, ad9222 - 65
ad9222 data sheet rev. f | page 18 of 60 90 85 80 75 70 65 60 1 1000 100 10 snr/sfdr (db) analog input frequency (mhz) sfdr snr 05967-029 figure 39 . snr/sfdr vs. f in , ad9222 - 50 snr/sfdr (db) frequency (mhz) 1 10 100 1000 50 55 60 65 70 75 80 85 90 2v p-p, sfdr 2v p-p, snr 05967-095 figure 40 . snr/sfdr vs. f in , ad9222 - 65 100 90 95 85 80 75 70 65 60 ?40 ?20 0 20 40 60 80 sinad/sfdr (db) temperature (c) 2v p-p, sfdr 2v p-p, sinad 05967-030 figure 41 . sinad/sfdr vs. temperature, f in = 2.61 mhz, ad9222 - 50 90 85 80 75 70 65 60 ?40 ?20 0 20 40 80 60 sinad/sfdr (db) temperature (c) 2v p-p, sfdr 2v p-p, sinad 05967-096 figure 42 . sinad/sfdr vs. temperature, f in = 2.3 mhz, ad9222 - 65 90 85 80 75 70 65 60 ?40 ?20 0 20 40 60 80 sinad/sfdr (db) temperature (c) 2v p-p, sfdr 2v p-p, sinad 05967-031 figure 43 . sinad/sfdr vs. temperature, f in = 20.1 mhz, ad9222 - 50 90 85 80 75 70 65 60 ?40 ?20 0 20 40 80 60 sinad/sfdr (db) temperature (c) 2v p-p, sfdr 2v p-p, sinad 05967-097 figure 44 . sinad/sfdr vs. temperature, f in = 19.7 mhz, ad9222 - 65
data sheet ad9222 rev. f | page 19 of 60 05967-036 code inl (lsb) ?1.0 1.0 0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.8 0.6 0.4 0.2 500 1000 1500 2000 2500 3000 3500 4000 figure 45 . inl, f in = 2.3 mhz, ad9222 - 50 code inl (lsb) ?1.0 1.0 0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.8 0.6 0.4 0.2 500 1000 1500 2000 2500 3000 3500 4000 05967-098 fi gure 46 . inl, f in = 35 mhz, ad9222 - 65 0.6 0.8 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0 4000 3500 3000 2500 2000 1500 1000 500 dnl (lsb) code 05967-099 figure 47 . dnl, f in = 2.3 mhz, ad9222 - 50 0.6 0.8 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0 4000 3500 3000 2500 2000 1500 1000 500 dnl (lsb) code 05967-099 figure 48 . dnl, f in = 35 mhz, ad9222 - 65 05967-056 frequency (mhz) cmrr (db) ?70 ?30 0 5 10 15 20 25 30 35 40 ?65 ?60 ?55 ?50 ?45 ?40 ?35 figure 49 . cmrr vs. freq uency, ad9222 - 50 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 n n ? 1 n ? 2 n ? 3 n + 1 n + 2 n + 3 number of hits (millions) code 0.27 lsb rms 05967-038 figure 50 . input - referred noise histogram, ad9222 - 50
ad9222 data sheet rev. f | page 20 of 60 2.5 0 0.5 1.0 1.5 2.0 number of hits (millions) code n n + 1 n + 2 n + 3 n ? 3 n ? 2 n ? 1 0.3 lsb rms 05967-100 figure 51 . input - referred noise histogram, ad9222 - 65 amplitude (dbfs) ?120 0 ?20 ?40 ?60 ?80 ?100 0 5 10 15 20 25 frequency (mhz) npr = 60.3db notch = 18.0mhz notch width = 3.0mhz 05967-041 figure 52 . noise power ratio (npr), ad9222 - 50 0 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 500 450 400 350 300 250 200 150 100 50 amplitude (dbfs) frequency (mhz) ?3db bandwidth = 325mhz 05967-040 figure 53 . full - power bandwidth vs. frequency, ad9222 - 50
data sheet ad9222 rev. f | page 21 of 60 theory of operation the ad9222 architecture consists of a pipelined adc divided into three sections: a 4 - bit first sta ge followed by eight 1.5 - bit stages and a final 3 - bit flash. each stage provides sufficient overlap to correct for flas h errors in the preceding stage . the quantized outputs from each stage are combined into a final 12- bit result in the digital correction logic. the pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consis ts of a low resolution flash adc connected to a switched - capacitor dac and an interstage residue amplifier ( for example, a multiplying digital - to - analog converter ( mdac ) ). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects error s, and passes the data to the output buffers. the data is then serialized and aligned to the frame and data clocks . analog input conside rations the analog input to the ad9222 is a differential switched - capacitor c ircuit designed for processing differential input signals. th is circuit can support a wide common - mode range while maintain ing exce l lent performance. an input common - mode voltage of midsupply minimizes signal - dependent e r rors and provides optimum performan ce. s s h c par c sample c sample c par v i n ? x h s s h v i n + x h 05967-043 figure 54 . switched - capacitor input circuit the clock signal alternately switches the input circuit between sa m ple mode and hold mode (see figure 54 ). when the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving so urce. in addition, low - q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the adc. such use of low - q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a shunt capacitor or two single - ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low - pass filter at the i n put to limit unwanted broadband noise. see the an - 742 application note , the an - 827 application note , and the analog dialogue article transformer - coupled front - end for wideband a/d converters (volume 39, april 2005) for more information . in general, the precise values depend on the appl i cation. the analog inputs of the ad9222 are not internally dc - biased. therefore, i n ac - coupled applications, the user must provide this bias exte r nally. setting the device so that v cm = av dd /2 is recom mended for optimum perfor m ance, but the device can function over a wider range with reaso n able performance, as shown in figure 55 and figure 57.
ad9222 data sheet rev. f | page 22 of 60 90 85 80 75 70 65 60 0.2 1.6 1.4 1.2 1.0 0.8 0.6 0.4 snr/sfdr (db) analog input common-mode voltage (v) sfdr (dbc) snr (db) 05967-044 figure 55 . snr/sfdr vs. common - mode voltage, f in = 2.3 mhz, ad9222 - 50 90 85 80 75 70 65 60 0.2 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 snr/sfdr (db) analog input common-mode voltage (v) sfdr (dbc) snr (db) 05967-101 figure 56 . snr/sfdr vs. common - mode voltage, f in = 2.3 mhz, ad9222 - 65 90 85 80 75 70 65 60 0.2 1.6 1.4 1.2 1.0 0.8 0.6 0.4 snr/sfdr (db) analog input common-mode voltage (v) sfdr (dbc) snr (db) 05967-042 figure 57 . snr/sfdr vs. common - mode voltage, f in = 35 mhz, ad9222 - 50 90 85 80 75 70 65 60 0.2 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 snr/sfdr (db) analog input common-mode voltage (v) sfdr (dbc) snr (db) 05967-102 figure 58 . snr/sfdr vs. common - mode volta ge, f in = 35 mhz, ad9222 - 65
data sheet ad9222 rev. f | page 23 of 60 for best dynamic performance, the source impedances driving vin + x and vin ? x should be matched such that common - mode settling errors are symmetrical. these errors are reduced by the common - mode rejection of the adc. an internal reference buffer creates the positive and negative reference voltages, reft and refb, respectively, that define the span of the adc core. the output common - mode of the reference buffer is set to midsupply, and the reft and refb voltages and span a re defined as reft = 1/2 ( avdd + vref ) refb = 1/2 ( avdd ? vref ) span = 2 ( reft ? refb ) = 2 vref it can be seen from these equations that the reft and refb voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the vref voltage. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the ad9222 , the largest input span available is 2 v p - p. differential input configurations there are several w ays to drive the ad9222 either actively or passively ; however, optimum performance is achieved by driving the analog input differentially. f o r example , using the ad8 334 differential driver to drive the ad9222 pr o vides excellent performance and a flexible interface to the adc (see figure 62 ) for baseband applications. this configuration is common ly used for medical ultrasound systems. for applications where snr is a key p arameter, differential transfor mer coupling is the recommended input configuration (see figure 59 and figure 60 ) because the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9222 . regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. 2v p-p r r c diff 1 c 1 c diff is optional. 49.9 0.1f 1k 1k a gnd a vdd adt1?1wt 1:1 z r a tio vin ? x adc ad9222 vin + x c 05967-046 figure 59 . differential transformer - coupled configuration for baseband applications adc ad9222 2v p-p 2.2pf 1k ? 0.1f 1k 1k a vdd adt1?1wt 1:1 z r a tio 16nh 16nh 0.1f 16nh 33 ? 33 ? 499 ? 65 ? vin + x vin ? x 05967-047 figure 60 . differential transformer - coupled configuration for if applications si ngle - ended input configuration a single - ended input may provide adequate performance in cost - sensitive applications. in this configuration, sfdr and distortion performance degrade due to the large input common - mode swing. if the application requires a sing le - ended input configuration, ensure that the source i m pedances on each input are well matched in order to achieve the best possible performance. a full - scale input of 2 v p - p can still be applied to the adcs vin + x pin while the vin ? x pin is terminated. figure 61 details a typical single - ended input configuration. 2v p-p r r 49.9 0.1f 0.1f a vdd 1k 25 1k 1k 1k a vdd vin ? x adc ad9222 vin + x c diff 1 c 1 c diff is optional. c 05967-048 figure 61 . single - ended input configuration 05967-049 ad8334 1.0k 1.0k 374 187 r r c 0.1f 187 0.1f 0.1f 0.1f 0.1f 10f 0.1f 1v p-p 0.1f lna 120nh vga voh vip inh 22pf lmd vin lop lon vol 18nf 274 vin ? x adc ad9222 vin + x 1k 1k avdd figure 62 . differential input configuration u sing the ad8334
ad9222 data sheet rev. f | page 24 of 60 clock input consider ations for optimum performance, the ad9222 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. t his s ignal is typically ac - coupled to the clk+ and clk? pins via a transformer or capacitors. these pins are biased i n ternally and require no add i tional bias ing . figure 63 shows a preferred method for clocking the ad9222 . the low jitter clock source is converted from a single - ended signal to a differential signal using an rf transformer. the back - to - back schottky diodes across the secondary transformer limit clock excursions into the ad9222 to approximately 0.8 v p - p diffe r ential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9222 , and i t preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottk y diodes: hsm2812 clk+ 50? 100? clk? clk+ adc ad9222 mini-circuits ? adt1-1w t , 1:1z xfmr 05967-050 figure 63 . transformer - coupled differential clock a nother option is to ac - couple a differential pecl signal to the sample cloc k input pins as shown in figure 64 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 family of clock drivers o f fers excellent jitter performance. clk+ 10 0? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? clk? ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 50 ? 1 50 ? 1 clk clk 1 50 ? resis t ors are optional. clk? clk+ adc ad9222 05967-051 pec l driver figure 64 . differential pecl sample clock clk+ clk? 10 0? 0.1f 0.1f 0.1f 0.1f 50? 1 l vds driver 50? 1 clk clk 1 50? resis t ors are optional. clk? clk+ adc ad9222 05967-052 ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 figur e 65 . differential lvds sample clock in some applicat ions, it is acceptable to drive the sample clock inputs with a single - ended cmos signal. in such applications, clk+ should be directly driven from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f c a pacitor in parallel with a 39 k? r esistor (see figure 66 ). although the clk+ input circuit supply is avdd (1.8 v), this input is designed to withstand input voltages of up to 3.3 v, making the sele c tion of the drive logic voltage very flexible. clk+ 0.1f 0.1f 0.1f 39 k ? cmos driver 50 ? 1 o p t i on a l 100 ? 0.1f clk clk 1 50? resistor is optional. clk? clk+ adc ad9222 05967-053 ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 figure 66 . single - ended 1.8 v cmos sample clock clk+ 0.1f 0.1f 0.1f cmos driver 5 0 ? 1 o p t i on a l 100? clk clk 1 50 ? resis t or is optional. 0.1f clk? clk+ adc ad9222 05967-054 ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 figure 67 . single - ended 3.3 v cmos sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signa ls. as a result, these adcs may be sens i tive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9222 contains a duty cycle s tab i lizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nom i nal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the perfor m ance of the a d9222 . when the dcs is on, noise and distortion perfor - mance are nearly flat for a wide range of duty c y cles. however, some applications may require the dcs function to be off. if so, keep in mind that the dynamic range performance can be affected when op erated in this mode. see the memory map section for more details on using this feature. the duty cycle stabilizer uses a delay - locked loop (dll) to create the nonsampling edge. as a result, any changes to the sampling fr e quency require approximately eight clock cycles to allow the dll to acquire and lock to the new rate.
data sheet ad9222 rev. f | page 25 of 60 clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input fr e quency ( f a ) due only to aperture jitter ( t j ) can be calc u lated by snr d egradation = 20 log 10( 1/2 f a t j ) in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if unde r sampling applications are particularly sensitive t o jitter (see figure 68). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9222 . power supplies for clock dri vers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal - controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other met h ods), it should be retimed by the original clock at the last step. refer to the an - 501 application note and the an - 756 application note for m ore in - depth information about jitter performance as it relates to adcs. 1 10 100 1000 16 b i t s 14 b i t s 12 b i t s 30 40 50 60 70 80 90 100 1 10 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps a n a l og i npu t f reque n cy (m h z) 10 bits 8 bits rms clock jitter requirement snr (db) 05967-055 figure 68 . ideal snr vs. input frequency and jitter power dissipation and power - down mode as shown in figure 69 , the power dissi pated by the ad9222 is proportional to its sample rate. the digital power dissipation does not vary much b e cause it is determined primarily by the drvdd supply and bias current of the lvds output drivers. 05967-057 encode (msps) current (a) 10 50 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 15 20 25 30 35 40 45 0.500 0.550 0.600 0.650 0.700 0.750 0.800 power (w) total power avdd current drvdd current fig ure 69 . supply current vs. f sample for f in = 10.3 mhz, ad9222 - 50 encode (msps) current (ma) 10 60 50 20 30 40 700 750 800 850 900 950 power (mw) total power avdd current drvdd current 0 50 100 150 200 250 300 350 400 450 500 05967-103 figure 70 . supply current vs. f sample for f in = 10.3 mhz, ad9222 - 65
ad9222 data sheet rev. f | page 26 of 60 by asserting the pdwn pin high, the ad9222 is placed in to power - down mode. in this state, the adc typically dissipates 11 m w. d u r i n g p o w e r - down, the lvds output drivers are placed in a high impedance state. the ad9222 returns to n ormal oper a ting mode when the pdwn pin is pulled low. this pin is both 1.8 v and 3.3 v tolerant. in power - down mode, low power dissipation is achieved by shutting down the reference, reference buffer, pll, and biasing networks. the decoupling capacitors on reft and refb are discharged when entering power - down mode and must be recharged when r e turning to normal operation. as a result, the wake - up time is related to the time spent in the power - down mode; shorter cycles result in proportionally shorter wake - up times. with the recommended 0.1 f and 4.7 f decoupling capacitors on reft and refb, approximately 1 sec is required to fully discharge the reference buffer decoupling capacitors , and approximately 375 s is required to restore full operation. there are several other power - down options available when using the spi. the user can individually power down each channel or put the entire device into standby mode. th e latter option allows the user to keep the internal pll powered when fast wake - up times (~600 ns ) are required. see the memory map section for more details on using these features. digital outputs and timing the ad9222 differential outputs conform to the ansi - 644 lvds standard on default power - up. this can be changed to a low power, reduced signal option ( similar to the ieee 1596.3 standard ) via the sdio/odm pin or spi. this lvds standard can further reduce the overall power dissipation of the device by approximately 36 m w. see the sdio/odm pin section or table 16 in the memory map section for more information. the lvds driver current is derived on c hip and sets t he output current at each ou tput equal to a nominal 3.5 ma. a 100 ? differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. the ad9222 lvds outputs facilitate interfacing wi th lvds receivers in custom asics and fpgas for superior switching performance in noisy environments. single point - to - point net topologies are recommended with a 100 ? termination resistor placed as clos e to the receiver as possible. if there is n o far - en d receiver termination or there is poor differential trace routing , timing errors may result . to avoid such timing errors, i t is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together an d at equal lengths. an example of the fco and data stream with proper trace length and position is shown in figure 71. ch1 500mv/div = fco ch2 500mv/div = dco ch3 500mv/div = data 5.0ns/div 05967-058 figure 71 . lvds output timing example in ansi - 644 mode (default), ad9222 - 50 ch1 500mv/div = fco ch2 500mv/div = dco ch3 500mv/div = data 5.0ns/div 05967-084 fi gure 72 . lvds output timing example in ansi - 644 mode (default), ad9222 - 65
data sheet ad9222 rev. f | page 27 of 60 an example of the lvds output using the ansi - 644 standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths less than 2 4 inches on standard fr - 4 material is shown in figure 73 and figure 74 . figure 75 and figure 76 show example s of trace lengths exceed ing 24 inches on standard fr - 4 material. notice that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is the user s responsibility to determine if the waveforms meet the timing budget of the d esign when the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal ter mination (increasing the current) of all eight outputs in order to drive longer trace lengths (see figure 77 and figure 78 ). even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the drvdd supply increases when thi s option is used. in cases that require inc reased driver strength to the dco and fco outputs because of load mismatch, register 0x15 allows the user to increase the drive strength by 2. to do this, set the appropriate bit in register 0x 5. note that this feature cannot be used with bit 4 and bit 5 in register 0x 15. bit 4 and bit 5 take precedence over this feature. see the memory map section for more details. 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?1.0ns ?1.5ns ?0.5ns 0ns 0.5ns 1.0ns 1.5ns eye diagram voltage (mv) eye: all bits uls: 12071/12071 90 50 10 20 30 40 60 70 80 0 ?150ps ?100ps ?50ps 0ps 50ps 100ps 150ps tie jitter histogram (hits) 05967-061 figure 73 . data eye for lvds outputs in ansi - 644 mode with trace lengths less than 24 inches on standard fr - 4, ad9222 - 50 600 400 200 ?600 ?400 ?200 0 ?1.0ns ?1.5ns ?0.5ns 0ns 0.5ns 1.0ns 1.5ns eye diagram voltage (mv) eye: all bits uls: 9596/15596 20 40 60 80 100 140 120 0 ?150ps ?100ps ?50ps 0ps 50ps 100ps 150ps tie jitter histogram (hits) 05967-106 figure 74 . data eye for lvds outputs in ansi - 644 mode with trace lengths less than 24 inches on standard fr - 4, ad9222 - 65 60 80 90 70 50 40 20 10 100 30 0 ?200ps ?100ps 100ps 0ps 200ps tie jitter histogram (hits) 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?1.0ns ?0.5ns 0ns 0.5ns 1.5ns ?1.5ns 1.0ns eye diagram voltage (mv) eye: all bits uls: 12067/12067 05967-059 figure 75 . data eye for lvds outputs in ansi - 644 mode with trace lengths greater than 24 inches on standard fr - 4, ad9222 - 50
ad9222 data sheet rev. f | page 28 of 60 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?1.0ns ?1.5ns ?0.5ns 0ns 0.5ns 1.0ns 1.5ns eye diagram voltage (mv) eye: all bits uls: 7591/15591 20 40 60 80 100 140 120 0 ?300ps ?200ps ?100ps 0ps 100ps 200ps 300ps tie jitter histogram (hits) 05967-105 figure 76 . data eye for lvds outputs in ansi - 644 mode with trace lengths greater than 24 inches on standard fr - 4, ad9222 - 65 400 300 200 100 ?400 ?300 ?200 ?100 0 ?0.5ns 0ns 0.5ns eye diagram voltage (mv) eye: all bits uls: 12072/12072 80 50 10 20 30 40 60 70 0 ?150ps ?100ps ?50ps 0ps 50ps 100ps 150ps tie jitter histogram (hits) ?1.0ns 1.5ns ?1.5ns 1.0ns 05967-060 figure 77 . data eye for lvds outputs in ansi - 644 mode with 100 ? termination on and trace lengths greater than 24 inches on standard fr - 4, ad9222 - 50 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?1.0ns ?1.5ns ?0.5ns 0ns 0.5ns 1.0ns 1.5ns eye diagram voltage (mv) eye: all bits uls: 8000/15600 20 40 60 80 100 140 120 0 ?200ps ?100ps 0ps 100ps 200ps 300ps tie jitter histogram (hits) 05967-104 figure 78 . data eye for lvds outputs in ansi - 644 mode with 100 ? termination on and trace lengths greater than 24 inches on stan dard fr - 4, ad9222 - 65 the format of the output data is offset binary by default. an example of the output coding format can be found in table 8 . t o change the output data format to twos complement, see the memory map section. table 8 . digital output coding code (vin + x ) ? (vin ? x ), input span = 2 v p - p (v) digital output offset binary (d11 ... d0) 4095 +1.00 1111 1111 1111 2048 0.00 1000 0000 0000 2047 ?0.000488 0111 1111 1111 0 ?1.00 0000 0000 0000 data from each adc is serialized and provided on a separate c hannel. the data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 780 mbps (12 bits 65 msps = 78 0 mbps). the lowest typical conversion rate is 10 msps. however, if lower sample rates are required for a specif ic application, the pll can be set up via the spi to allow encode rates as low as 5 msps. see the memory map section to enable this feature.
data sheet ad9222 rev. f | page 29 of 60 two output clocks are provided to assist in capturing data from the ad9222 . the dco is used to clock the output data and is equal to six times the sampl e clock (clk) rate. data is clocked out of the ad9222 and must be captured on the rising and fallin g edges of the dco that supports double data rate (ddr) capturing. the fco is used to signal the start of a new output byte and is equal to the sampl e clock rate. see the timing diagram shown in figure 2 for more information. t able 9 . flex ible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 (8 - bit) 10 000 0 0000 (10 - bit) 1000 0000 0000 (12 - bit) 10 0000 0000 0000 (14 - bit) same yes 0010 +full - scale short 1111 1111 (8 - bit) 11 1111 1111 (10 - bit) 1111 1111 1111 (12 - bit) 11 1111 1111 1111 (14 - bit) same yes 0011 ?full - scale short 0000 0000 (8 - bit) 00 0000 0000 (10 - bit) 0000 0000 0000 (12 - bit) 00 0000 0000 0000 (14 - bit) same yes 0100 checker board 1010 1010 (8 - bit) 10 1010 1010 (10 - bit) 1010 1010 1010 (12 - bit) 10 1010 1010 1010 (14 - bit) 0101 0101 (8 - bit) 01 0101 01 01 (10 - bit) 0101 0101 0101 (12 - bit) 01 0101 0101 0101 (14 - bit) no 0101 pn sequence long 1 n/a n/a yes 0110 pn sequence short 1 n/a n/a yes 0111 one - /zero - word toggle 1111 1111 (8 - bit) 11 1111 1111 (10 - bit) 1111 1111 1111 (12 - bit) 11 1111 1111 1111 (14 - bit) 0000 0000 (8 - bit) 00 0000 0000 (10 - bit) 0000 0000 0000 (12 - bit) 00 0000 0000 0000 (14 - bit) no 1000 user input register 0x19 to register 0x1a register 0x1b to register 0x1c no 1001 1 -/ 0 - bit toggle 1010 1010 (8 - bit) 10 1010 1010 (10 - bit) 1010 1010 1010 (12 - bit) 10 1010 1010 1010 (14 - bit) n/a no 1010 1 sync 0000 1111 (8 - bit) 00 0001 1111 (10 - bit) 0000 0011 1111 (12 - bit) 00 0000 0111 1111 (14 - bit) n/a no 1011 one bit high 1000 0000 (8 - bit) 10 0000 0000 (10 - bit) 1000 000 0 0000 (12 - bit) 10 0000 0000 0000 (14 - bit) n/a no 1100 mixed frequency 1010 0011 (8 - bit) 10 0110 0011 (10 - bit) 1010 0011 0011 (12 - bit) 10 1000 0110 0111 (14 - bit) n/a no 1 all test mode options except pn sequ ence short and pn sequence long can support 8 - to 14 - bit word lengths in order to verify data capture to the receiver.
ad9222 data sheet rev. f | page 30 of 60 when the spi is used , the dco phase can be adjusted in 60 increments relative to t he data edge. this enables the user to refine system timing margins if required. the default dco + and dco? timing, as shown in figure 2 , is 90 relative to the output data edge. an 8 - , 10 - , and 14 - bit serial stream can also be i nitiated from the spi. this allows the user to implement and test compatibility with lower and higher resolution systems. when changing the resolution to an 8 - or 10 - bit serial stream, the data stream is shortened. see figure 3 for the 10 - bit example. however, when using the 14 - bit option, the data stream stuffs two 0s at the end of the 14 - bit serial data. when the spi is used , all of the data outputs can also be inverted from their nominal state. this is not to be confused with inverting the serial stream to an lsb - first mode. in default mode, as shown in figure 2 , the msb is first in the data output serial stream. however, this can be inverted so that the lsb is first in the data output serial stream ( see figure 4 ). there are 12 digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing. refer to table 9 for the output bit sequencing options available. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. note that some patterns may not adhere to the data format select option. in a ddition, user - defined test patterns can be assigned in the 0x19, 0x1a, 0x1b, and 0x1c register addresses. all test mode options except pn sequence short and pn sequence long can support 8 - to 14 - bit word lengths in order to verify data capture to the rece iver. the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 or 511 bits. a description of the pn sequence and how it is generated can be found in s ection 5.1 of the itu - t 0.150 (05/96) standard. t he only differ ence is that the starting value must be a specific value instead of all 1 s (s ee table 10 for the initial values ) . the pn s equence l ong pattern produces a pseudorandom bit sequence that repeats itself every 2 23 ? 1 or 8,388,607 b its. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu - t 0.150 (05/96) standard. the only differences are that the starting value must be a specific value instead of all 1s (see table 1 0 for the initial values) and the ad9222 inverts the bit stream with relation to the itu standard. table 10. pn sequence sequence initial value first three output samples (msb first ) pn sequence short 0x0df 0xdf9, 0x353, 0x301 pn sequence long 0x29b80a 0x591, 0xfd7, 0x0a3 consult the memory map section for information on how to change these additional digital output timing features through the spi . sdio/odm pin the sdio/odm pin is for use in applications that do not require spi mode operation. this pin can enable a low power, reduced signal option ( similar to the ieee 1596.3 reduced range link output standard ) if it and the csb pin are tied to avdd during device power - up. this option should only be used when the digital output trace lengths are less than 2 inches from the lvds receiver. when this option is used, t he fco, dco, and outputs function normally, but the lvds signal swing o f all channels is reduced from 350 mv p - p to 200 mv p - p , allowing the user to further reduce the power on the drvdd supply. for applications where this pin is not used, it should be tied low. in this case, the device pin can be left open, and the 30 k? internal pull - down resistor pulls this pin low. this pin is only 1.8 v tolerant. if applications require this pin to be driven from a 3.3 v logic level, insert a 1 k? resistor in series with this pin to limit the current. table 11 . output driver mode pin settings selected odm odm voltage resulting output standard resulting fco and dco normal operation 10 k? to agnd ansi - 644 (default) ansi - 644 (default) odm avdd low power, reduced signal option low power, reduced s ignal option sclk/dtp pin th e sclk/dtp pin is for use in applications that do not require spi mode operation. th is pin can enable a single digital test pattern if it and the csb pin are held high during device power - up. when the sclk/ dtp is tied to avdd, the adc channel outputs shift out the following pattern: 1000 0000 0000. the fco and dco function normally while all channels shift out the repeatable test pattern. this pattern allows the user to perform timing alignment adjustments among the fco, dco, a nd output data. for normal operation, this pin should be tied to agnd through a 10 k? resistor. this pin is both 1.8 v and 3.3 v tolerant. table 12 . digital test pattern pin settings selected dtp dtp voltage resulting d + x and d ? x resulting fco and dco normal operation 10 k? to agnd normal operation normal operation dtp avdd 1000 0000 0000 normal operation additional and custom test patterns can also be observed when commanded from the spi port. consult the memory map section for information about the options available.
data sheet ad9222 rev. f | page 31 of 60 csb pin the csb pin should be tied to avdd for applications that do not require spi mode operation. by tying csb high, all sclk and sdio information is ignored. this pin is both 1.8 v and 3.3 v tolerant. rbias pin to set the internal core bias current of the adc, place a resistor (nominally equal to 10.0 k ?) to ground at the rbias pin. the resistor current is derived on - chip and sets t he avdd current of the adc to a nominal 450 ma at 65 msps. therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance voltage reference a stable , accurate 0.5 v voltage reference is built into the ad9222 . this is gained up internally by a factor of 2, setting v ref to 1.0 v, which results in a full - scale differential input span of 2 v p - p. the v ref is set internally by default; however, the vref pin can be driven externally with a 1.0 v reference to improve accuracy. when applying the decoupling capacitors to the vref, reft, and refb pins, use ceramic low - esr capacitors. these capacitors should be close to the adc pins and on the same layer of the pcb as the ad9222 . the recommended capacitor values and configurations for the ad9222 refere nce pin are shown in figure 79. table 13 . reference settings selected mode sense voltage resulting vref (v) resulting differential span (v p - p) external reference avdd n/a 2 external reference inte rnal, 2 v p - p fsr agnd to 0.2 v 1.0 2.0 internal reference operation a comparator within the ad9222 detects the potential at the sense pin and configures the reference. if sense is grounded, the reference am plifier switch is connected to the internal resistor divider (see figure 79 ), setting vref to 1 v. the reft and refb pins establish their input span of the adc core from the reference configuration. the analog input full - scale r ange of the adc equals twice the voltage at the reference pin for either an internal or an external reference configuration. if the reference of the ad9222 is used to drive multiple converters to improve gain m atching, the loading of the refe r - ence by the other converters must be considered. figure 81 depicts how the internal reference voltage is affected by loa d ing. 1f 0.1f vref sense 0.5v reft 0.1f 0.1f 4.7f 0.1f refb select logic adc core + vin ? x vin + x 05967-064 figure 79 . internal reference configurat ion 1f 1 0.1f 1 vref sense avdd 0.5v reft 0.1f 0.1f 4.7f 0.1f refb select logic adc core + vin ? x vin + x external reference 1 optional. 05967-065 figure 80 . external reference operation
ad9222 data sheet rev. f | page 32 of 60 external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift chara c - teristics. figure 82 shows the typical drift characteri s tics of the internal reference in 1 v mode. when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. the external reference is loaded with an equival ent 6 k? load. an internal reference buffer generates the positive and negative full - scale references, reft and refb, for the adc core. therefore, the external refe r ence must be limited to a nominal of 1.0 v. 0 1.0 0.5 2.0 1.5 3.0 2.5 3.5 v ref error (%) current load (ma) 05727-083 ?30 ?5 ?10 ?15 ?20 ?25 5 0 figure 81 . v ref accu racy vs. load, ad9222 - 5 0 0.02 ?0.18 ?0.14 ?0.10 ?0.06 ?0.02 ?0.16 ?0.12 ?0.08 ?0.04 0 ?40 v ref error (%) temperature (c) 05967-028 ?20 0 20 40 60 80 figure 82 . typical v ref drift, ad9222 - 5 0
data sheet ad9222 rev. f | page 33 of 60 serial port interfac e (spi) the ad9222 serial port interface allows the user to configure the converter for specif ic functions or operations through a structured register space provided inside the adc. this gives the user added flexibility and customization , depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided down into fields, as doc - umented in the memory map section. detailed operational information can be found in the an - 877 application note , interfacing to high speed adcs via spi . there are three pins that define the spi : sclk, sdio, and csb (see table 14) . the sclk pin is used to synchronize the read and write data presented to the adc. the sdio pin is a dual - purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb pin is an active low control that enables or disables the read and write cycles. table 14 . serial port pins pin function sclk serial clock. the serial shift clock in put . sclk is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual - purpose pin. the typical role for this pin is an input or output, depending on the instruct ion sent and the relative position in the timing frame. csb chip select bar (active low). this control gates the read and write cycles. the falling edge of the csb in conjunction with the rising edge of the sclk determines the start of the framing seque nce. during an instruction phase, a 16 - bit instruction is transmitted followed by one or more data bytes, w hich is determined by bit field w0 and bit field w1. an example of the serial timing and its definitions can be found in figure 84 and table 15 . during normal operation, csb is used to signal to the device that spi commands are to be received and processed. when csb is brought low, the device processes sclk and sdio to process instructions. nor mally, csb remains low until the communication cycle is complete. however, if connected to a slow device, csb can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. csb can be stalled when t ransferring one, two, or three bytes of data. when w0 and w1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until csb is taken high to end the communication cycle. this allows complete memory trans fers without requiring additional instructions. regardless of the mode, if csb is taken high in the middle of a byte transfer, the spi state machine is reset and the device waits for a new instruction. in addition to the operation modes, the spi port confi guration influences how the ad9222 operate s . for applications that do not require a control port, the csb line can be tied and held high. this places the remainder of the spi pins in to their secondary mode s, as defined in the sdio/odm pin and sclk/dtp pin section s . csb can also be tied low to enable 2 - wire mode. when csb is tied low, sclk and sdio are the only pins required for communication. although the devic e is synchronized during power - up, the user should ensure that the serial port remains synchronized with the csb line when using this mode . when operating in 2 - wire mode, it is recommended to use a 1 - , 2 - , or 3 - byte transfer exclusively. without an active csb line, streaming mode can be entered but not exited. in addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on - chip memory. if the instruction is a readback operation, performing a readback causes the sdio pin to change from an input to an output at the appropriate point in the serial frame. data can be sent in msb - or lsb - first mode. msb - first mode is the def ault at power - up and can be changed by adjusting the configuration register. for more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi .
ad9222 data sheet rev. f | page 34 of 60 hardware interface the pins described in table 14 compose the physical interface between the users programming device and the serial port of the ad9222 . the sclk and csb pins function as in puts when using the spi. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. if multiple sdio pins share a common connection, care should be taken to ensure that proper v oh levels are met. assuming t he same load for each ad9222 , figure 83 shows the number of sdio pins that can be connected together and the resulting v oh level. 05967-037 number of sdio pins connected together v oh (v) 1.715 1.720 1.725 1.730 1.735 1.740 1.745 1.750 1.755 1.760 1.765 1.770 1.775 1.780 1.785 1.790 1.795 1.800 0 30 20 10 40 50 60 70 80 90 100 figure 83 . sdio pin loa ding this interface is flexible enough to be controlled by either serial proms or pic mirocontrollers , providing the user with an alternative method, other than a full spi controller, to program the adc (see the an - 812 application note ). if the user chooses not to use the spi, these dual - function pins serve their secondary functions when the csb is strapped to avdd during device power - up. see the theory of operation section for detail s on which pin - strappable functions are supported on the spi pins.
data sheet ad9222 rev. f | page 35 of 60 don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t hi t clk t lo t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 05967-068 figure 84 . serial timing details table 15 . serial timing definitions parameter timing ( minimum , ns) description t ds 5 set up time betw een the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 set up time between csb and sclk t h 2 hold time between csb and sclk t hi 16 minimum period that sclk should be in a l ogic high state t lo 16 minimum period that sclk should be in a logic low state t en_sdio 10 minimum time for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 84) t dis_sdio 10 minimum time for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 84)
ad9222 data sheet rev. f | page 36 of 60 memory map reading the memory m ap table each row in the memory map register table ( table 16) has eight address locations. the memory map is divided into three sections: the chip configuration register map (address 0x00 to address 0x02), the device index and transfer register map (address 0x05 and address 0xff), and the adc fu nctions register map (address 0x08 to address 0x2 2 ). the left most column of the memory map indicates the register address number , and t he default value is shown in the second right - most column. the (msb) bit 7 column is the start of the default hexadecima l value given. for example, address 0x09, the c lock register , has a default value of 0x01 , mean ing bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. this setting is the default for the duty cycle stabilizer in the on condition. by writing a 0 to bit 6 of this address, the duty cycle stabilizer turns off. for more information on this and other functions, consult the an - 877 application note , interfa cing to high speed adcs via spi . reserved locations undefined memory locations should not be written to except when writing the default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power - up. default values when the ad9222 c om es out of a reset, critical registers are preloaded with default values. these values are indicated in table 16 , where an x refers to an undefined feature. logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, clear a bit is synonymous with bit is se t to logic 0 or writing logic 0 for the bit.
data sheet ad9222 rev. f | page 37 of 60 table 16 . memory map register addr. (hex) parameter name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) default notes/ comments chip configuratio n register s 00 chip_port_config 0 lsb first 1 = on 0 = off (default) soft reset 1 = on 0 = off (default) 1 1 soft reset 1 = on 0 = off (default) lsb first 1 = on 0 = off (default) 0 0x18 the nibbles should be mirrored so that lsb - or msb - first mode is set cor - rectly regard less of shift mode. 01 chip_id 8 - bit chip id bits 7:0 (ad9222 = 0x07), (default) read only default is unique chip id, different for each device. this is a read - only register. 02 chip_grade x child id [ 6:4 ] (identify device variants o f chip id) 000 = 65 msps 011 = 50 msps 001 = 40 msps x x x x read only child id used to differentiate graded devices. device index and transfer registers 04 device_index_2 x x x x data channel h 1 = on (default) 0 = off data channel g 1 = on (default) 0 = off data channel f 1 = on (default) 0 = off data channel e 1 = on (default) 0 = off 0x0f bits are set to determine which on - chip device receives the next write command. 05 device_index_1 x x clock channel dco 1 = on 0 = off (default) clock channel fc o 1 = on 0 = off (default) data channel d 1 = on (default) 0 = off data channel c 1 = on (default) 0 = off data channel b 1 = on (default) 0 = off data channel a 1 = on (default) 0 = off 0x0f bits are set to determine which on - chip device receives the next write command. ff device_update x x x x x x x sw transfer 1 = on 0 = off (default) 0x00 synchronously transfers data from the master shift register to the slave. adc functions 08 modes x x x x x internal power - down mode 000 = chip run (default) 001 = full power - down 010 = standby 011 = reset 0x00 determines various generic modes of chip operation. 09 clock x x x x x x x duty cycle stabilizer 1 = on (default) 0 = off 0x01 turns the internal duty cycle stabilizer on and off. 0d test_io user test mod e 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once reset pn long gen 1 = on 0 = off (default) reset pn short gen 1 = on 0 = off (default) output test mode see table 9 in the digital outputs and timing section 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checker board output 0101 = pn 23 sequence 0110 = pn 9 sequence 0111 = one - /zero - word toggle 1000 = user input 1001 = 1 - /0 - bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode ) 0x00 when this reg - ister is set, the test data is placed on the output pins in place of normal data.
ad9222 data sheet rev. f | page 38 of 60 addr. (hex) parameter name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) default notes/ comments 14 output_mode x 0 = lvds ansi - 644 (default) 1 = lvds low power, (ieee 1596.3 similar) x x x output invert 1 = on 0 = off (default) 00 = offset binary (default) 01 = twos complement 0x00 configures the outputs and the format of the data. 15 output_adjust x x output driver termination 00 = none (d efault) 01 = 200 ? 10 = 100 ? 11 = 100 ? x x x dco and fco 2 drive strength 1 = on 0 = off (default) 0x00 determines lvds or other output properties. primarily func - tions to set the lvds span and common - mode levels in place of an external resistor. 16 output_phase x x x x 0011 = output clock phase adjust (0000 through 1010) 0000 = 0 relative to data edge 0001 = 60 relative to data edge 0010 = 120 relative to data edge 0011 = 180 relative to data edge (default) 0101 = 300 relative to data edge 0110 = 360 relative to data edge 1000 = 480 relative to data edge 1001 = 540 relative to data edge 1010 = 600 relative to data edge 1011 to 1111 = 660 relative to data edge 0x03 on devices that utilize global clock divide, determines which phase of the di vider output is used to supply the output clock. internal latching is unaffected. 19 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user - defined pattern, 1 lsb. 1a user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user - defined pattern, 1 msb. 1b user_patt2 _lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user - defined pattern, 2 lsb. 1c user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user - defined pattern, 2 msb. 21 serial_control lsb first 1 = on 0 = off (default) x x x <10 msps, low encode rate mode 1 = on 0 = off (def ault) 000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 0x00 serial stream control. default causes msb first and the native bit stream (global). 22 serial_ch_stat x x x x x x channel output reset 1 = on 0 = off (default) channel power - down 1 = on 0 = off (default) 0x00 used to power down individual sections of a converter (local).
data sheet ad9222 rev. f | page 39 of 60 power and ground recommendations when connecting power to the ad9222 , it is rec ommended that two separate 1.8 v supplies be used: one for analog (avdd) and one for digital (drvdd). if only one supply is available, it should be routed to the avdd first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the drvdd. the user can employ several different decoupling capacitors to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts , with minimal trace le ngth s. a single pc board ground plane should be sufficient when using the ad9222 . with proper decoupling and smart parti - tioning of the pc boards analog, digital, and clock sections, optimum performance can be easily achieved. exposed paddle thermal heat slug recommendations it is required that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9222 . an exposed continuous copper plane on the pcb should mate to the ad9222 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be so lder - filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process , whereas using one continuous plane with no partitions only guarantees one tie point. see figure 85 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . silkscreen p artition pin 1 indic a t or 05967-069 figure 85 . typical pcb layout
ad9222 data sheet rev. f | page 40 of 60 evaluation board the ad9222 evaluation board provides all of the support cir - cuitry required to operate the adc in its various modes and configuratio ns. the converter can be driven differentially using a transformer (default) or an ad8334 driver. the adc can also be driven in a single - ended fashion. separate power pins are provided to isolate the dut from t he drive circuitry of the ad8334 . each input configuration can be selected by changing the connection of various jumpers (see figure 90 to figure 94 ). figure 86 shows the typical bench characterization setup used to evaluate the ac performance of the ad9222 . it is critical that the signal sources used for the analog input and clock ha ve very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specif ied noise performance. see figure 90 to figure 100 for the complete schematics and layout diagrams demonstrat ing the routing and grounding techniques that should be applied at the system level. power supplies this evaluation board has a wall - mountable switching power supply that provides a 6 v, 2 a maximum output. c onnect the supply to the rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz. the other end of the supply is a 2.1 mm inner diameter jack that connects to the pcb at p701. once on the pc board, the 6 v supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. when operating the eval uation board in a nondefault condition, l701 to l704 can be removed to disconnect the switching power supply. this enables the user to bias each section of the board individually. use p702 to connect a different supply for each section. at least one 1.8 v supply is needed for av dd _dut and drvdd_dut; however, it is recommended that separate supplies be used for both analog and digital signals and that each supply have a current capability of 1 a . to operate the evaluation board using the vga option, a separa te 5.0 v analog supply (avdd_5 v) is needed. to operate the evaluation board using the spi and alter - nate clock options, a separate 3.3 v analog supply (avdd_3.3 v) is needed in addition to the other supplies. input signals when connecting the clock and a nalog source s to the evalu - ation board , use clean signal generators with low phase noise, such as rohde & schwarz sma or hp8644 signal generators or the equivalent , as well as a 1 m, shielded, rg - 58, 50 ? coaxial cable . enter the desired frequency and amplitude from the adc specifi - cations tables. typically, most analog devices , inc., evaluation boards can accept approximately 2.8 v p - p or 13 dbm sine wave input for the clock. when connecting the analog input source, it is recommended to use a multipole, narrow - band, band - pass filter with 50 ? terminations. good choices of such band - pass filters are available from tte, allen avionics, and k&l microwave, inc. the filter should be connected directly to the evaluation board if possible. output signals the default setup uses the analog devices hsc - adc - fifo5 - intz to interface with the analog devices standard dual - channel fifo data capture board (hcs - adc - evalcz). tw o of the eight chan nels can be evaluated at the same time. for more information on the channel settings and optional settings of these boards, www.analog.com/fifo . rohde & sch w arz, sma, 2v p-p signa l synthesizer rohde & sch w arz, sma, 2v p-p signa l synthesizer band- p ass fi l ter xfmr input clk ch a t o ch h 12-bit seria l l vds usb connection ad9222 ev alu a tion board interposer board hsc-adc-e v alcz fifo d at a capture board pc running adc ana l yzer and spi user soft w are 1.8v ? + ? + a vdd_dut a vdd_3.3v dr vdd_dut gnd gnd ? + 5.0v gnd a vdd_5v 1.8v 6v dc 2a max w al l outlet 100v t o 240v ac 47hz t o 63hz switching power supp l y ? + gnd 3.3v ? + vcc gnd 3.3v spi spi spi spi 05967-070 figure 86 . evaluation board connection
data sheet ad9222 rev. f | page 41 of 60 default operation an d jumper selection settings the following is a list of the default and optional settings or modes allowed on the ad9222 rev. a evaluation board. ? power: connect the switching power supply that is provided with the evaluation kit between a rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz and p701. ? ain: the evaluation board is set up for a transformer - coupled analog input with an optimum 50 ? impedance match of 150 mhz of bandwidth (see figure 87 ). for more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. the common mode of the analog inputs is develope d from the center tap of the transformer or avdd_dut/2. 0 amplitude (dbfs) frequency (mhz) 0 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 50 100 150 200 250 300 350 400 450 500 ?3d b cutoff = 15 0m hz 05967-071 figure 87 . evaluation board full - power bandwidth, ad9222 - 50 ? vref: vref is set to 1.0 v by tying the sense pin to ground, r317. this causes the adc to operate in 2.0 v p - p f ull - scale range. a separate external reference option using the adr510 or adr520 is also included on the e valuation board. p opulate r312 and r313 and remove c307. proper use of the vref options is noted in the voltage reference section. ? rbias: rbias has a default setting of 10 k? (r301) to ground and is used to set the adc core bia s current. ? clock: the default clock input circuitry is derived from a simple transformer - coupled circuit using a high bandwidth 1:1 impedance ratio transformer (t401) that adds a very low amount of jitter to the clock path. the clock input is 50 ? termi nated and ac - coupled to handle single - ended sine wave types of inputs. the transformer converts the single - ended input to a differential signal that is clipped before entering the adc clock inputs. a differential lvpecl clock can also be used to clock th e adc input using the ad9515 (u401). p opulate r406 and r407 with 0 ? resistors and remove r215 and r216 to disconnect the default clock path inputs. in addition, populate c205 and c206 with a 0.1 f capacitor and remove c409 and c410 to disconnect the default clock path outputs. the ad9515 has many pin - strappable options that are set to a default mode of operation . consult the ad9515 data sheet for more information about these and other options. in addition, an on - board osc illator is available on the osc4 01 and can act as the primary clock source. the setup is qu ick and involves installing r403 with a 0 ? resistor and setting the enable jumper (j401 ) to the on position. if the user wishes to employ a different oscillator, two oscillator footp rint options are available (osc4 01) to check the adc performance . ? pdwn: to enable the power - down feature, short j301 to the on position (avdd) on the pdwn pin. ? sclk/dtp: to enable the digital test pattern on the digital outputs of the adc, use j304. if j304 is tied to avdd during device power - up, test pattern 1000 0000 0000 is enabled. see the sclk/dtp pin section for details. ? sdio/odm: to enable the low power, reduced signal option ( similar to the ieee 1595.3 reduced range link lvds output standard ) , use j303. if j303 is tied to avdd during device power - up, it enables the lvds outp uts in a low power, reduced signal option from the default ansi - 644 standard. this option changes the signal swing from 350 mv p - p to 200 mv p - p, reducing the power of the drvdd supply. see the sdio/odm pin section for more det ails. ? csb: to enable processing of the spi information on the sdio and sclk pins , tie j302 low in the always enable mode . to ignore the sdio and sclk information, tie j302 to avdd. ? non - spi mode: for users who wish to operate the dut without using spi, remo ve jumpers j302, j303, and j304. this disconnects the csb, sclk/dtp, and sdio/od m pins from the control bus, allowing the dut to operate in its simplest mode. each of these pins has internal termination and will float to its respective level. ? d + x , d ? x : if an alternative data capture method to the setup shown in figure 90 is used, optional receiver terminations, r318 and r320 to r328, can be installed next to the high speed backplane connector.
ad9222 data sheet rev. f | page 42 of 60 alternative analog i nput drive configuration the following is a brief description of the alternative analog input drive configuration using the ad8334 dual vga. if this drive option is in use, some components may need to be populated, in wh ich case all the necessary components are listed in table 17 . for more details on the ad8334 dual vga, including how it works and its optional pin settings, consult the ad8334 data sheet. to configure the analog input to drive the vga instead of the default transformer option, the following components need to be removed and/or changed. ? remove r102, r115, r128, r141, r161, r162, r163, r16 4, r202, r208, r218, r225, r234 , r241, r252, r259, t101, t102, t103, t104, t201, t202, t203, and t204 in the default analog input path. ? populate r101, r114, r127, r140, r201, r217, r233 , and r251 with 0 ? resistors in the analog input path. ? populate r152, r153, r154, r155, r156, r157, r158, r159, r215, r216, r229, r230, r247, r248, r263, r264, c103, c105, c110, c112, c117, c119, c124, c126, c203, c205, c210, c212, c217, c219, c224, and c226 with 10 k? resistors to provide an input common - mode level to the a dc analog input s. ? populate r105, r113, r118, r124, r131, r137, r151, r160, r205, r213, r221, r222, r237, r238, r255, and r256 with 0 ? resistors in the adc analog input path to connect the vga outputs . ? remove r515, r520, r527, r532, r615, r620, r627, and r 632 on the ad8334 analog out put s. ? remove r512, r524, r612, and r624 to set the ad8334 mode and ad8334 hilo pin low. some applications may require this to be different. consult the ad8334 data sheet for more information on these functions. in this configuration , l505 to l520 and l605 to l620 are populated with 0 ? resistors to allow signal connection and use of a filter if additional requirements are necessary. in this example , a 16 mhz , two - pole low - pass filter was applied to the ad8334 outputs . t he following components ne ed to be removed and/or changed: ? remove l507, l508, l511, l512, l515, l516, l519, l520, l607, l608, l611, l612, l615, l616, l619, and l620 on the ad833 4 analog outputs . ? populate l507, l508, l511, l512, l515, l516, l519, l520, l607, l608, l611, l612, l615, l616, l619, and l620 with 680 nh inductors. ? populate c543, c547, c551, c555, c643, c647, c651, and c655 with a 68 pf capacitor. 68pf 680nh 680nh 05967-107 figure 88 . example filter configured for 16 mhz , two - pole low - pass filter 0 ?120 ?100 ?80 ?60 ?40 ?20 0 5.0 7.5 2.5 10.0 15.0 17.5 12.5 20.0 22.5 25.0 amplitude (dbfs) frequency (mhz) 05967-108 f sample = 50msps ain = 3.5mhz ad8334 = max gain setting figure 89 . ad9222 fft example results using 16 mhz, two - pole low - pass filter applied to the ad8334 outputs (f sample = 50 msps, ain = 3. 5 mhz, ad8334 = maximum gain setting , analog input signal = ? 1.03 dbfs, snr = 60.8 dbc, sfdr = 67.02 dbc )
data sheet ad9222 rev. f | page 43 of 60 dnp dnp dnp vga input ain ain ain vga input vga input connection connection connection connection vga input channel c ain dnp ain channel a ain ain channel b ain channel d r134 33 ? p105 p102 r148 1k ? r160 0??dnp r151 0??dnp r137 0??dnp r131 0??dnp r124 0??dnp r118 0??dnp r113 0??dnp r105 0??dnp r101 0??dnp r140 0??dnp r127 0??dnp r114 0??dnp r107 dnp 1 2 5 6 t104 1 2 3 4 3 4 5 6 t103 cm3 1 2 5 6 t101 1 2 3 4 3 4 5 6 t102 1 e102 1 e101 dnp c127 10 ? fb112 10 ? fb111 10 ? fb110 10 ? fb109 10 ? fb108 10 ? fb107 10 ? fb106 10 ? fb105 10 ? fb104 dnp c113 10 ? fb103 10 ? fb102 10 ? fb101 dnp c106 2.2pf c118 dnp c124 vin_d 0.1f c114 0.1f c107 vin_d vin_c vin_b vin_b avdd_dut avdd_dut cm2 cm1 ch_d ch_d cm3 cm1 inh4 inh3 inh1 ch_a ch_a ch_c cm4 avdd_dut avdd_dut avdd_dut cm4 avdd_dut inh2 ch_b ch_b cm2 ch_c r104 0? r116 0? r130 0? r143 0? avdd_dut avdd_dut avdd_dut avdd_dut avdd_dut avdd_dut dnp c120 0.1f c128 0.1f c121 0.1f c101 2.2pf c125 dnp c117 dnp c126 dnp c119 dnp c112 0.1f c108 0.1f c109 0.1f c116 0.1f c115 0.1f c122 0.1f c123 dnp c110 2.2pf c111 dnp c103 2.2pf c104 dnp c105 0.1f c102 vin_a vin_a cm1 cm2 1 e103 1 e104 cm3 cm4 r135 1k ? r123 1k ? r109 1k ? 499 ? r164 r163 499 ? r162 499 ? 499 ? r161 dnp r159 dnp r158 dnp r157 r156 dnp r108 33 ? dnp r152 dnp r155 dnp r154 dnp r153 r102 64.9 ? r147 33 ? r146 33 ? r145 dnp r149 1k ? r136 33 ? r133 dnp r132 dnp r125 1k ? r122 33 ? r121 33 ? r111 1k ? r106 dnp r112 1k ? r150 1k ? r139 1k ? r138 1k ? r126 1k ? r110 33 ? r141 64.9 ? r142 0? r128 64.9 ? r129 0? r115 64.9 ? r117 0? r103 0? r144 dnp r120 dnp r119 dnp p101 p106 p108 p107 p104 p103 vin_c 05967-072 dnp: do no t popul a te. figure 90 . evaluation board schematic, dut analog inputs
ad9222 data sheet rev. f | page 44 of 60 dnp dnp dnp dnp vga input ain ain ain ain vga input vga input vga input ain connection connection connection connection channel e dnp ain channel g ain channel h channel f ain 1 2 5 6 t204 r266 1k ? 10 ? fb212 r265 1k ? 10 ? fb209 10 ? fb207 r245 33 ? r240 dnp 1 2 5 3 4 3 4 6 t203 2.2pf c211 r231 1k ? 10 ? fb206 10 ? fb203 1 2 5 6 t202 r220 0? r257 dnp r258 dnp r224 dnp r223 dnp 2.2pf c204 r207 dnp r206 dnp 1 2 5 3 4 3 4 6 t201 10 ? fb201 r262 1k ? r256 0??dnp r255 0??dnp r238 0??dnp r237 0??dnp r222 0??dnp r221 0??dnp r213 0??dnp r205 0??dnp r201 0??dnp r251 0??dnp r233 0??dnp r217 0??dnp cm7 1 e202 1 e201 dnp c227 10 ? fb211 10 ? fb210 10 ? fb208 10 ? fb205 10 ? fb204 dnp c213 10 ? fb202 dnp c206 2.2pf c218 dnp c224 vin_h 0.1f c214 0.1f c207 vin_h vin_g vin_g vin_f vin_f avdd_dut avdd_dut cm6 cm5 ch_h ch_h cm7 cm5 inh8 inh7 inh5 ch_e ch_e ch_g cm8 avdd_dut avdd_dut avdd_dut cm8 avdd_dut inh6 ch_f ch_f cm6 ch_g r204 0? r236 0? r254 0? avdd_dut avdd_dut avdd_dut avdd_dut avdd_dut avdd_dut dnp c220 0.1f c228 0.1f c221 0.1f c201 2.2pf c225 dnp c217 dnp c226 dnp c219 dnp c212 0.1f c208 0.1f c209 0.1 f c216 0.1f c215 0.1f c222 0.1f c223 dnp c210 dnp c203 dnp c205 0.1f c202 vin_e vin_e cm5 cm6 1 e203 1 e204 cm7 cm8 r246 1k ? r228 1k ? r214 1k ? 499 ? r259 r241 499 ? r225 499 ? 499 ? r208 dnp r263 dnp r247 dnp r229 r215 dnp r209 33 ? dnp r216 dnp r264 dnp r248 dnp r230 r202 64.9 ? r261 33 ? r260 33 ? r239 dnp r227 33 ? r226 33 ? r211 1k ? r212 1k ? r250 1k ? r249 1k ? r232 1k ? r210 33 ? r242 33 ? r252 64.9 ? r253 0? r234 64.9k ? r235 0? r218 64.9 ? r219 0? r203 0? p201 p202 p205 p206 p208 p207 p203 p204 05967-073 dnp: do no t popul a te. figure 91 . evaluation board schematic, dut analog inputs (continued)
data sheet ad9222 rev. f | page 45 of 60 4.7f c w gn d vout trim/nc ad 9222bcpz-65 avdd clk+ clk? d+ b d+ c d+ d d+ e d+ f d+ g d+h d? b d? c d? d d? e d? f d? g d?h dco + dco ? drgnd drvdd fc o + fc o ? pdwn avdd r bia s refb reft sclk/dtp sdio/odm vin+a vi n+ c vi n+ d vi n+ e vin+g vin?a vin?b vi n? c vi n? d vi n? f vin?g vr ef vi n+ f slu g av d d avdd avdd drgnd vin?h d+a d?a vin+b csb se n se vi n? e vin+h drvdd avdd avdd avdd av d d avdd avdd avdd av d d a1 a10 a2 a3 a4 a5 a6 a7 a8 a9 b1 b10 b2 b3 b4 b5 b6 b7 b8 b9 c1 c10 c2 c3 c4 c5 c6 c7 c8 c9 d1 d10 d2 d3 d4 d5 d6 d7 d8 d9 gndab1 gndab10 gndab2 gndab3 gndab4 gndab5 gndab6 gndab7 gndab8 gndab9 gndcd1 gndcd10 gndcd2 gndcd3 gndcd4 gndcd5 gndcd6 gndcd7 gndcd8 gndcd9 optional output terminations digi ta l ou t pu t s using external vref v ref = 1v v ref = external v ref = 0.5v remove c214 when always enable spi odm enable dtp enable v ref = 0.5v(1 + r219/r220) vref select 1.0v reference decoupling optional ext ref pwdn enable nc r efe ren ce circ u it ry r318,r320?r328 dnp r322 chb 1 10 2 3 4 5 6 7 8 9 11 20 12 13 14 15 16 17 18 19 31 40 32 33 34 35 36 37 38 39 41 50 42 43 44 45 46 47 48 49 21 30 22 23 24 25 26 27 28 29 51 60 52 53 54 55 56 57 58 59 p301 chb dnp r318 dnp r320 dnp r321 dnp r323 dnp r324 dnp r325 dnp r328 dnp r326 3 2 1 j304 1 2 3 j303 1 2 3 j302 3 2 1 j301 r319 1k ? avdd_dut av dd_du t av dd_du t vi n_ e vi n_ e vi n_ f vi n_ f 1 5 9 4 42 45 48 5 1 6 2 7 10 9 11 8 3 2 3 0 2 8 2 2 2 0 1 8 16 3 1 2 9 2 7 2 1 1 9 1 7 15 2 4 2 3 13 36 14 35 37 2 6 2 5 33 34 40 47 5 5 6 1 5 6 41 12 5 4 5 7 5 8 38 39 43 4 9 5 3 6 0 2 44 46 5 0 5 2 6 3 3 5 6 6 4 0 u 30 1 r30 6 100 k? r30 5 100 k? r303 100k ? dnp r304 dnp r302 sclk_dtp sdio_odm csb_dut 0.1f c305 4.99k ? r309 1f c307 c301 0.1f c304 0.1f c302 0.1f adr510artz u302 10k ? r310 dnp r311 r30 7 10 k? vsense_dut 470k ? r308 dnp r313 dnp r312 0? r317 dnp r31 dnp r315 dnp r314 r30 1 10 k? 0.1f c306 avdd_dut vref_dut av dd_du t avdd_dut drvdd_dut avdd_dut av dd_du t avdd_dut clk clk ch b ch c ch d chh ch b ch c ch d chh dc o dc o gnd drvdd_dut fco fco vse n se _du t vin_h vin_h vi n_ c vi n_ d vin_g vi n_ c vi n_ d vin_g vr ef _du t ch g ch g ch f ch f ch e ch e avdd_dut avdd_dut gnd avdd_dut vin_a vin_a cha cha avdd_dut vin_b vin_b avdd_dut avdd_dut avdd_dut dnp r327 sclk_cha sdi_cha csb1_cha csb2_cha sdo_cha sclk_chb sdi_chb csb3_chb csb4_chb sdo_chb dco fco cha chc chd che chf chg chh chh chg chf che chd chc cha fco dco c303 05967-074 dnp: do no t popul a te. figure 92 . evaluation board schematic, dut, vre f, and digital output interface
ad9222 data sheet rev. f | page 46 of 60 crystal_3 gnd oe out vcc oe gnd out vcc clk clkb gn d gnd_pad out0 out0b out1 out1b r set s0 s1 s1 0 s2 s3 s4 s5 s6 s7 s8 s9 syncb vr ef vs signal=dnc;27,28 dnp dnp dnp dnp dnp dnp dnp dnp input encode enc enc clock circuit dnp dnp dnp dnp disable osc401 enable osc401 optional clock oscillator ad9515 pin?strap settings optional clock drive circuit lvpecl output dnp: do not populate. dnp dnp dnp lvds output clip sine out (default) dnp 1 2 6 7 2 5 8 1 6 9 1 5 1 0 1 4 1 1 1 3 3 2 5 18 19 23 22 3 2 1 3 1 3 3 u401 signal=avdd_3.3v;4,17,20,21,24,26,29,30 ad951 5bcpz 0? r430 r446 0? r424 r428 0? r425 0? r427 0? 1 2 3 j401 10 12 3 5 7 1 8 14 osc401 0? r426 s0 0? r436 r437 0? 10k ? r413 c401 0.1f r401 10k ? r403 0? dnp 0.1f 5 1 4 c 2 1 4 c 0.1f c416 c411 0.1f 0? r406 0? r415 10k ? r402 49.9 ? r411 r407 0? 0? r434 c405 0.1f dnp 0.1f c406 dnp 0.1f c407 dnp c408 0.1f dnp r444 0? 0? r442 r440 0? 0? r438 r432 0? 0? r445 r443 0? 0? r441 r439 0? r435 0? 0? r433 r431 0? 0? r429 s4 1 e401 avdd_3.3v 0? r416 3 2 1 cr401 hsms-2812-tr1g r414 4.12k ? s5 s3 s2 s1 avdd_3.3v r421 240 ? c409 0.1f r409 dnp 240 ? r420 6 5 4 3 2 1 t401 0.1f c402 c410 0.1f 49.9 ? r404 r410 10k ? r412 dnp dnp r408 r405 0? c403 0.1f 100 ? r423 r422 100 ? r418 0? r417 0? s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 opt_clk opt_clk clk avdd_3.3v opt_clk opt_clk clk clk clk avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v s6 s7 s8 s9 s10 c413 0.1f0.1f 8 1 4 c 4 1 4 c 0.1f 0.1f c417 avdd_3.3v avdd_3.3v p401 p402 05967-075 0.1f figure 93 . evaluation board schematic, clock circuitry
data sheet ad9222 rev. f | page 47 of 60 c w c w ad833 4acpz-reel inh2 lmd2 com2x lon2 lop2 vip2 vin2 vps2 vps3 vin3 vip3 lop3 lon3 com3x lmd3 inh3 co m4 i nh 4 l md4 co m4 x lon 4 lo p4 vip 4 vi n 4 vps4 h i l o mode vps1 vi n 1 vip 1 lo p1 lon 1 co m1 x l md1 i nh 1 co m1 n c nc vol2 voh2 co m2 vc m 2 co m3 vc m 3 vol3 voh3 vc m 4 voh4 vol4 vol1 voh1 vc m 1 gain12 cl mp1 2 en1 2 com12 vps12 com12 en3 4 com34 vps34 com34 cl mp3 4 gain34 ext vg exte r nal vari ab l e ga i n d r i ve vari ab l e ga i n c i r cu it ( 0? 1.0v dc ) hilo pin=h=+/? 75mv hilo pin=lo=+/? 50mv rclamp pin ext vg hilo pin=h=+/? 75mv hilo pin=lo=+/? 50mv rclamp pin exte r nal var i ab l e ga i n d r i ve v ariabl e gai n c irc u i t ( 0? 1.0v dc ) resistors or design your own filter. power down enable (0?1v=disable power) dnp: do not populate. mode pin positive gain slope = 0?1.0v negitive gain slope = 2.25?5.0v populate l505?l520 with 0 ? 0.1f c537 0? l519 0? l515 374 ? r532 374 ? r527 dnp r522 dnp r517 0.1f c530 0.1f c529 0.1f c528 120nh l503 0.1f c524 0.1f c523 0.1f c518 374 ? r515 10k ? r50 4 0.1f c50 4 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 33 34 35 36 37 38 39 41 42 43 44 45 46 47 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 6 3 6 4 48 40 u501 0.1f c506 avdd_5v 10k ? r51 1 10k ? r51 2 10k ? r50 5 avdd _5 v avdd_5v avdd_5v av dd_5 v vg3 4 0.1f c538 avdd_5v avdd_5v 0.1f c50 5 22pf c50 3 vg1 2 c51 2 10 f avdd_5v avdd _5 v 0.1f c50 1 187 ? r51 3 10k ? dnp r506 10k ? r501 274 ? r50 3 0.018f c50 2 1 2 jp501 120nh l501 0.1f c508 0.1f c50 9 1000pf c507 39k ? r502 c51 0 10 f av dd_5 v vg12 vg12 g n d r521 dnp 0? l510 r516 dnp c542 dnp 187 ? r518 187 ? r514 0.1f c545 0.1f c541 0.1f c540 0? l505 0? l511 0? l508 0? l507 0? l509 0? l506 0? l512 374 ? r520 187 ? r519 0.1f c544 c546 dnp c543 dnp c547 dnp ch_c ch_d ch_d ch_c dnp r534 r533 dnp 0? l518 r528 dnp c550 dnp 187 ? r530 187 ? r526 0.1f c553 0.1f c549 0.1f c548 0? l513 0? l516 0? l517 0? l514 0? l520 187 ? r531 187 ? r525 0.1f c552 c554 dnp c551 dnp c555 dnp dnp r529 ch_a ch_b ch_b ch_a inh4 0.1f c51 1 22pf c51 4 0.1f c51 3 120nh l502 inh3 274 ? r50 7 0.018f c51 5 0.1f c522 22pf c52 0 0.1f c51 9 274 ? r50 8 0.018f c52 1 inh2 c52 6 22pf c52 5 0.1f l504 120nh r50 9 274 ? c52 7 0.018f inh1 0.1f 0.1f c536 c535 c534 c533 10f 10 f 10k ? dnp r510 0.1f c532 1000pf c531 10k ? r535 1 jp502 39k ? r536 av dd_5 v vg34 vg34 g n d 10k ? r52 3 10k ? r52 4 avdd_5v 05967-076 2 figure 94 . evaluation board schematic, optional dut analog input dri ve
ad9222 data sheet rev. f | page 48 of 60 c w c w ad833 4acpz-reel inh2 lmd2 com2x lon2 lop2 vip2 vin2 vps2 vps3 vin3 vip3 lop3 lon3 com3x lmd3 inh3 co m4 i nh 4 l md4 co m4 x lon 4 lo p4 vip 4 vi n 4 vps4 h i l o mode vps1 vi n 1 vip 1 lo p1 lon 1 co m1 x l md1 i nh 1 co m1 n c nc vol2 voh2 co m2 vc m 2 co m3 vc m 3 vol3 voh3 vc m 4 voh4 vol4 vol1 voh1 vc m 1 gain12 cl mp1 2 en1 2 com12 vps12 com12 en3 4 com34 vps34 com34 cl mp3 4 gain34 mode pin positive gain slope = 0?1.0v negative gain slope = 2.25?5.0v ext vg exte r nal vari ab l e ga i n d r i ve vari ab l e ga i n c i r cu it ( 0? 1.0v dc ) hilo pin=h=+/? 75mv hilo pin=lo=+/? 50mv rclamp pin ext vg hilo pin=h=+/? 75mv hilo pin=lo=+/? 50mv rclamp pin exte r nal var i ab l e ga i n d r i ve v ariabl e gai n c irc u i t ( 0? 1.0v dc ) populate l605?l620 with 0 ? resistors or design your own filter. power down enable (0?1v=disable power) dnp: do not populate. 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 33 34 35 36 37 38 39 41 42 43 44 45 46 47 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 6 3 6 4 48 40 u601 374 ? r620 dnp r636 374 ? r632 374 ? r627 dnp r622 0 ? l619 0 ? l611 0.1f c630 0.1f c629 0.1f c628 0.1f c624 0.1f c623 0.1f c618 0.1f c616 10k? r60 4 0.1f c60 4 10k? r61 2 10k? r62 4 avdd _5 v avdd_5v avdd_5v av dd_5 v vg7 8 0.1f c617 avdd_5v avdd_5v 0.1f c60 5 22pf c60 3 0.1f c606 vg5 6 c61 2 10 f avdd_5v avdd _5 v 0.1f c60 1 187 ? r61 3 10k? dnp r606 10k? r601 274 ? r60 3 0.018f c60 2 1 2 jp601 l601 120nh 0.1f c608 0.1f c60 9 10k? r60 5 1000pf c607 39k ? r602 c61 0 10 f av dd_5 v vg56 vg56 g n d r621 dnp 0 ? l610 r616 dnp c642 dnp 374 ? r615 187 ? r618 187 ? r614 0.1f c645 0.1f c641 0.1f c640 0 ? l605 0 ? l608 0 ? l607 0 ? l609 0 ? l606 0 ? l612 187 ? r619 0.1f c644 c646 dnp c643 dnp c647 dnp dnp r617 ch_g ch_h ch_h ch_g r633 dnp 0 ? l618 r628 dnp c650 dnp 187 ? r630 187 ? r626 0.1f c653 0.1f c649 0.1f c648 0 ? l613 0 ? l616 0 ? l615 0 ? l617 0 ? l614 0 ? l620 187 ? r631 187 ? r625 0.1f c652 c654 dnp c651 dnp c655 dnp dnp r629 ch_e ch_f ch_f ch_e inh8 0.1f c61 1 22pf c61 4 0.1f c61 3 l602 120nh inh7 274 ? r60 7 0.018f c61 5 0.1f c622 22pf c62 0 0.1f c61 9 l603 120nh 274 ? r60 8 c62 1 inh6 c62 6 22pf c62 5 0.1f l604 120nh r60 9 274 ? c62 7 0.018f inh5 0.1f 0.1f c636 10f c634 c633 10 f 10k ? dnp r610 0.1f c632 1000pf c631 10k? r634 1 2 jp602 39k ? r635 av dd_5 v vg78 vg78 g n d 10k? r61 1 avdd_5v 10k? r62 3 avdd_5v c635 05967-077 0.018f figure 95 . evaluation board schematic, optional dut analog input drive (continued)
data sheet ad9222 rev. f | page 49 of 60 nanosmdc110f-2 s2a-tp gp0 gp1 gp2 gp4 gp5 vdd vss mclr/gp3 pic12f629-i/sng 4 y1 vcc y2 a2 gnd a1 con005 7.5v power 2.5mm jack p1 p2 p3 p4 p5 p6 p7 p8 gn d gn d gn d gn d out y1 vcc y2 a2 gnd a1 optional +3.3v = normal operation = avdd_3.3v +5v = programming = avdd_5v reset/ reprogram isp pic programming header remove when using or programming pic (u402) spi circuitry from fifo power supply input input 6v, 2a max +5.0v dnp: do not populate. +1.8v +1.8v +3.3v decoupling capacitors optional power d702 6 5 4 3 2 1 u703 nc7wz16p6x_nl 3.3v_avdd 5v_avdd dut_avdd dut_drvdd l701 10h avdd_5v 1 2 3 4 u707 adp3339zakc?1.8-rl avdd_5v avdd_dut cr 70 2 gr een mc lr /gp3 cr 70 1 gr een 4 2 3 1 adp3339zakc?5-rl7 u706 1 2 3 4 u704 adp3339zakc?1.8-rl 4 2 3 1 adp3339zakc?3.3-rl u705 2 4 3 1 fer701 1 2 3 4 5 6 7 8 p702 dn p 1 3 2 p701 1 2 3 4 5 6 nc7w207p6x_nl u702 1k ? r713 0? r70 9 r70 8 0? 0? 0? r706 2 4 6 8 1 0 9 7 5 3 1 j702 1 2 3 s701 4 3 7 6 5 2 8 1 u701 0.1f c726 0.1f c742 avdd_dut 0.1f c730 d701 f701 avdd_3.3v 0.1f c740 0.1f c741 l702 10h c710 0.1f c709 10f 10h l705 r716 261 ? 10h l706 l704 10h c715 1f 0.1f c708 0.1f c712 c706 0.1f c717 1f c716 1f c714 1f pwr_in pwr_in 10f c707 c705 10f 10f c711 dut_avdd dut_drvdd 0.1f c735 0.1f c734 0.1f c733 0.1f c727 0.1f c732 0.1f c731 0.1f c743 0.1f c723 0.1f c725 0.1f c724 10h l703 5v_avdd 3.3v_avdd pwr_in pwr_in 1f c719 1f c721 1f c722 1f c720 l708 10h l707 10h drvdd_dut 1k ? r712 1k ? r710 r707 c701 0.1f r715 10k? 10k? r711 0 . 1 f c70 3 r704 0 ? ?dnp 0 ? ?dnp r703 0 ? ?dnp r705 261 ? r702 3 2 1 j701 r701 4.7k ? 1 e701 c70 2 0 . 1 f 10k? r714 pi c v c c gp1 gp0 mc lr /gp3 pi c v c c avdd_dut avdd_3.3v avdd_5v avdd_dut sclk_dtp csb_dut avdd_3.3v gp0 c sb 1_ch a scl k _ch a sd i _ch a gp1 s do_ch a avdd_dut sdio_odm pwr_in avdd_3.3v avdd_5v avdd_dut drvdd_dut 0.1f c744 0.1f c748 0.1f c747 0.1f c746 0.1f c745 0.1f c752 0.1f c753 0.1f c749 0.1f c751 0.1f c750 c704 10f 05967-078 in in out out out sk33-t p out in in out out out figure 96 . evaluation board schematic, power supply inputs and spi interface circuitry
ad9222 data sheet rev. f | page 50 of 60 05967-079 figure 97 . evaluation board layout, primary side
data sheet ad9222 rev. f | page 51 of 60 05967-080 figure 98 . evaluation board layout, ground plane
ad9222 data sheet rev. f | page 52 of 60 05967-081 figure 99 . evaluation board layout, power plane
data sheet ad9222 rev. f | page 53 of 60 05967-082 figure 100 . evaluation board la yout, secondary side (mirrored image)
ad9222 data sheet rev. f | page 54 of 60 table 17 . evaluation board bill of materials (bom) 1 item qnty. per board r eference d esignator device pkg. value mfg. mfg. part number 1 1 ad9222 -65 ebz pcb pcb pcb 2 118 c101, c102, c107, c108, c109, c114, c115, c116, c121, c122, c123, c128, c201, c202, c207, c208, c209, c214, c215, c216, c221, c222, c223, c228, c301, c302, c304, c305, c306, c401, c402, c403, c409, c410, c411, c412, c413, c414, c415, c416, c417, c418, c501, c 504, c505, c506, c508, c509, c511, c513, c518, c519, c522, c523, c524, c525, c528, c529, c530, c532, c534, c536, c537, c538, c601, c604, c605, c606, c608, c609, c611, c613, c616, c617, c618, c619, c622, c623, c624, c625, c628, c629, c630, c632 , c634, c636, c701, c702, c703, c706, c708, c710, c712, c723, c724, c725, c726, c727, c730, c731, c732, c733, c734, c735, c740, c741, c742, c743, c744, c745, c746, c747, c748, c749, c750, c751, c752, c753 capacitor 402 0.1 f, ceramic, x5r, 10 v, 10% tol murata grm155r71c104ka88d 3 8 c104, c111, c118, c125, c204, c211, c218, c225 capacitor 402 2.2 pf, ceramic, cog, 0.25 pf tol, 50 v murata grm1555c1h2r20cz01d 4 8 c510, c512, c533, c535, c610, c612, c633, c635 capacitor 805 10 f, 6.3 v 10% ceramic, x5r murata grm219r60j106ke19d 5 1 c303 capacitor 603 4.7 f, ceramic, x5r, 6.3 v, 10% tol murata grm188r60j475ke19d 6 4 c507, c531, c607, c631 capacitor 402 1000 pf, ceramic, x7r, 25 v, 10% tol murata grm155r71h102ka01d 7 8 c502, c515, c521, c527, c602, c615, c621, c627 capacitor 402 0.018 f, ceramic, x7r, 16 v, 10% tol avx 0402yc183kat2a
data sheet ad9222 rev. f | page 55 of 60 item qnty. per board r eference d esignator device pkg. value mfg. mfg. part number 8 8 c503, c514, c520, c526, c603, c614, c620, c626 capacitor 402 22 pf, ceramic, npo, 5% tol, 50 v murata grm1555c1h220jz01d 9 1 c704 capacito r 1206 10 f, tantalum, 16 v, 20% tol rohm tca1c106m8r 10 9 c307, c714, c715, c716, c717, c719, c720, c721, c722 capacitor 603 1 f, ceramic, x5r, 6.3 v, 10% tol murata grm188r61c105ka93d 11 16 c540, c541, c544, c545, c548, c549, c552, c553, c640, c641, c644, c645, c648, c649, c652, c653 capacitor 805 0.1 f, ceramic, x7r, 50 v, 10% tol murata grm21br71h104ka01l 12 4 c705, c707, c709, c711 capacitor 603 10 f, ceramic, x5r, 6.3 v, 20% tol murata grm188r60j106me47d 13 1 cr401 diode sot -23 30 v, 20 ma, dual schottky avago technologies hsms - 2812 - tr1g 14 2 cr701, cr702 led 603 green, 4 v, 5 m candela panasonic lnj314g8tra 15 1 d702 diode do - 214ab 3 a, 30 v, smc micro commercial co. sk33 - tp 16 1 d701 diode do - 214aa 5 a, 50 v, smc micro comme rcial co. s2a - tp 17 1 f701 fuse 1210 6.0 v, 2.2 a trip - current resettable fuse tyco/raychem nanosmdc110f - 2 18 1 fer701 choke coil 2020 10 h, 5 a, 50 v, 190 ? @ 100 mhz murata dlw5bsn191sq2l 19 24 fb101, fb102, fb103, fb104, fb105, fb106, fb107, fb108, fb109, fb110, fb111, fb112, fb201, fb202, fb203, fb204, fb205, fb206, fb207, fb208, fb209, fb210, fb211, fb212 ferrite bead 6 03 10 ? , test frequency 100 mhz, 25% tol, 500 ma murata blm18ba100sn1d 20 4 jp501, jp502, jp601, jp602 connector 2 - pin 100 mil header jumper, 2 - pin samtec tsw - 102-07 - g -s 21 6 j301, j302, j303, j304, j401, j701 connector 3 - pin 100 mil header jumper, 3 - pin samtec tsw - 103-07 - g -s 23 1 j702 connector 10- pin 100 mil header, male, 2 5 double row straight samtec tsw - 105-08 - g -d 24 8 l701, l702, l703, l704, l705, l706, l707, l708 ferrite bead 1210 10 h, bead core 3.2 2.5 1.6 smd, 2 a murata blm3 1pg500sn1l 25 8 l501, l502, l503, l504, l601, l602, l603, l604 inductor 402 120 nh, test freq 100 mhz, 5% tol, 150 ma murata lqg15hnr12j02d
ad9222 data sheet rev. f | page 56 of 60 item qnty. per board r eference d esignator device pkg. value mfg. mfg. part number 26 32 l505, l506, l507, l508, l509, l510, l511, l512, l513, l514, l515, l516, l517, l518, l519, l520, l60 5, l606, l607, l608, l609, l610, l611, l612, l613, l614, l615, l616, l617, l618, l619, l620 resistor 805 0 ? , 1/8 w, 5% tol nic components corp. nrc04z0trf 27 1 osc401 oscillator smt clock oscillator, 50.00 mhz, 3.3 v, 5% duty cycle valphey fisher vfac3h -l - 50mhz 28 9 p101, p103, p105, p107, p201, p203, p205, p207, p401 connector sma side - mount sma for 0.063" board thickness johnson components 142- 0701 - 851 29 1 p301 connector header 1469169 - 1, right angle 2 - pair, 25 mm, header assembly tyco 6469169 - 1 30 1 p701 connector 0.1", pcmt rapc722, power supply connector switchcraft rapc722x 31 21 r301, r307, r401, r402, r410, r413, r504, r505, r511, r512, r523, r524, r604, r605, r611, r612, r623, r624, r711, r714, r715 resistor 402 10 k ? , 1/16 w, 5% tol nic components corp. nrc04j103trf 32 18 r103, r117, r129, r142, r203, r219, r235, r253, r317, r405, r415, r416, r417, r418, r706, r707, r708, r709 resistor 402 0 ? , 1/16 w, 5% tol nic components corp. nrc04z0trf 33 8 r102, r115, r128, r141, r202, r218, r234, r252 resistor 402 64.9 ? , 1/16 w, 1% tol nic components corp. nrc04f64r9trf 34 8 r104, r116, r130, r143, r204, r220, r236, r254 resistor 603 0 ? , 1/10 w, 5% tol nic components corp. nrc06z0trf 35 28 r109, r111, r112, r123, r125, r126, r135, r138, r139, r148, r149, r150, r211, r212, r214, r228, r231, r232, r246, r249, r250, r262, r265, r266, r319, r710, r712, r713 resistor 402 1 k ? , 1/16 w, 1% tol nic components corp. nrc04f1001trf 36 16 r108, r110, r 121, r122, r134, r136, r146, r147, r209, r210, r226, r227, r242, r245, r260, r261 resistor 402 33 ? , 1/16 w, 5% tol nic components corp. nrc04j330trf
data sheet ad9222 rev. f | page 57 of 60 item qnty. per board r eference d esignator device pkg. value mfg. mfg. part number 37 8 r161, r162, r163, r164, r208, r225, r241, r259 resistor 402 499 ? , 1/16 w, 1% tol nic comp onents corp. nrc04f4990trf 38 3 r303, r305, r306 resistor 402 100 k ? , 1/16 w, 1% tol nic components corp. nrc04f1003trf 39 1 r414 resistor 402 4.12 k?, 1/16w, 1% tol nic components corp. nrc04f4121trf 40 1 r404 resistor 402 49.9 ? , 1/16 w, 0.5% to l susumu rr0510r - 49r9-d 41 1 r309 resistor 402 4.99 k ? , 1/16 w, 5% tol nic components corp. nrc04f4991trf 42 5 r310, r501, r535, r601, r634 potentiometer 3 - lead 10 k ? , cermet trimmer potentiometer, 18 turn top adjust, 10%, 1/2 w copal electronics c t94ew103 43 1 r308 resistor 402 470 k ? , 1/16 w, 5% tol nic components corp. nrc04j474trf 44 4 r502, r536, r602, r635 resistor 402 39 k ? , 1/16 w, 5% tol nic components corp. nrc04j393trf 45 16 r513, r514, r518, r519, r525, r526, r530, r531, r613, r614, r618, r619, r625, r626, r630, r631 resistor 402 187 ? , 1/16 w, 1% tol nic components corp. nrc04f1870trf 46 8 r515, r520, r527, r532, r615, r620, r627, r632 resistor 402 374 ? , 1/16 w, 1% tol nic components corp. nrc04f3740trf 47 8 r503, r 507, r508, r509, r603, r607, r608, r609 resistor 402 274 ? , 1/16 w, 1% tol nic components corp. nrc04f2740trf 48 11 r425,r427, r429, r431, r433, r435, r436, r439, r441, r443, r445 resistor 201 0 ? , 1/20 w, 5% tol nic components corp. nrc02z0trf 49 1 r701 resistor 402 4.7 k ? , 1/16 w, 1% tol nic components corp. nrc04j472trf 50 1 r702 resistor 402 261 ? , 1/16 w, 1% tol nic components corp. nrc04f2610trf 51 1 r716 resistor 603 261 ? , 1/16 w, 1% tol nic components corp. nrc06f261otrf 52 2 r4 20, r421 resistor 402 240 ? , 1/16 w, 5% tol nic components corp. nrc04j241trf 53 2 r422, r423 resistor 402 100 ? , 1/16 w, 1% tol nic components corp. nrc04f1000trf 54 1 s701 switch smd light touch, 100ge, 5 mm panasonic evq - plda15
ad9222 data sheet rev. f | page 58 of 60 item qnty. per board r eference d esignator device pkg. value mfg. mfg. part number 55 9 t101, t102, t103, t104, t201, t202, t203, t204, t401 transformer cd542 adt1 - 1wt+, 1:1 impedance ratio transformer mini - circuits adt1 - 1wt+ 56 2 u704, u707 ic sot - 223 adp33339akc - 1.8 - rl, 1.5 a, 1.8 v ldo regulator analog devices adp3339akcz - 1.8-rl 57 2 u501, u60 1 ic cp -64-3 ad8334acpz - reel, ultralow noise precision dual vga analog devices ad8334acpz - reel 58 1 u706 ic sot - 223 adp33 39akc -5 -rl7 analog devices adp3339akcz -5 -rl 59 1 u705 ic sot - 223 adp33 39akc - 3.3-rl analog devices adp3339akcz - 3.3-rl 60 1 u301 ic cp -64-3 ad9222bcpz - 65 , octal, 12 - bit, 50 msps serial lvds 1.8 v adc analog devices ad9222bcpz -65 61 1 u302 ic sot -23 adr510artz, 1.0 v, precision low noise shunt voltage reference analog devices adr510artz 62 1 u401 ic lfcsp cp -32-2 ad9515bcpz, 1.6 ghz clock distribution ic analog devices ad9515bcpz 63 1 u702 ic sc70, maa06a nc7wz07p6x_nl, uhs dual buffer fairchild nc7wz07p6x_nl 64 1 u703 ic sc70, maa06a nc7wz16p6x_nl, uhs dual buffer fairchild nc7wz16p6x_nl 65 1 u701 ic 8 - soic flash prog mem 1kx14, ram size 64 8, 20 mhz speed, pic12f controller series microchip pic12f629 - i/sng 1 this bom is rohs c ompliant .
data sheet ad9222 rev. f | page 59 of 60 outline dimensions complian t to jedec standar ds mo-22 0-vm md-4 0.22 min t o p v i e w 8.75 bsc sq 9.00 bsc sq 1 6 4 1 6 1 7 4 9 4 8 3 2 3 3 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max sea ting plan e pin 1 indica t or 7.55 7.50 sq 7.45 pin 1 ind ica t or 0.30 0.23 0.18 for proper connect ion of the expo sed pad, refe r to the pin conf igur atio n and func tion desc ript ions sect ion of this data sheet. 02- 23- 201 0-b e x p o s e d p a d ( b o t t o m v i e w ) figure 101 . 64 - lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp - 64 - 6) dimension s shown in millimeters ordering guide mode l 1 , 2 temperature range package description package option ad9222abcpz -40 ?40 c to +85c 64- lead lead frame chip scale package [lfcsp_vq] cp -64-6 ad9222abcpzrl7 - 40 ?40 c to +85c 64- lead lead frame chip scale package [lfcsp_vq] 7" tape and reel cp -64-6 ad9222abcpz -50 ?40 c to +85c 64- lead lead frame chip scale package [lfcsp_ vq] cp -64-6 ad9222abcpzrl7 - 50 ?40 c to +85c 64- lead lead frame chip scale package [lfcsp_vq] 7" tape and reel cp -64-6 ad9222abcpz -65 ?40 c to +85c 64- lead lead frame chip scale package [lfcsp_vq] cp -64-6 ad9222abcpzrl7 - 65 ?40 c to +85c 64- lead lead f rame chip scale package [lfcsp_vq] 7" tape and reel cp -64-6 ad9222 - 65ebz evaluation board 1 z = rohs compliant part. 2 the i nterposer b oard (hsc - adc - fifo5 - intz) is required to connect to the hsc - adc - eva lcz data capture board .
ad9222 data sheet rev. f | page 60 of 60 notes ? 2006 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their r espective owners. d05967 - 0 - 12/11(f)

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